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Commit 08d0e875 authored by Mahesh Kumar's avatar Mahesh Kumar Committed by Maarten Lankhorst
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drm/i915/skl+: nv12 workaround disable WM level 1-7 



Display Workaround #0826 (SKL:ALL BXT:ALL) & #1059(CNL:A)
Hardware sometimes fails to wake memory from pkg C states fetching the
last few lines of planar YUV 420 (NV12) planes. This causes
intermittent underflow and corruption.
WA: Disable package C states or do not enable latency levels 1 through 7
(WM1 - WM7) on NV12 planes.

v2: Addressed review comments by Maarten.

v3: Adding reviewed by tag from Shashank Sharma

v4: Added reviewed by from Juha-Pekka Heikkila

v5: Rebased the series

Reviewed-by: default avatarJuha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: default avatarShashank Sharma <shashank.sharma@intel.com>
Reviewed-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: default avatarMahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: default avatarVidya Srinivas <vidya.srinivas@intel.com>
Signed-off-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1523245273-30264-9-git-send-email-vidya.srinivas@intel.com
parent 8b2b53ce

drivers/gpu/drm/i915/intel_pm.c

+11 −0
Original line number Diff line number Diff line
@@ -4653,6 +4653,17 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, 
		}

	}



	/*

	 * Display WA #826 (SKL:ALL, BXT:ALL) & #1059 (CNL:A)

	 * disable wm level 1-7 on NV12 planes

	 */

	if (wp->is_planar && level >= 1 &&

	    (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||

	     IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))) {

		result->plane_en = false;

		return 0;

	}



	/* The number of lines are ignored for the level 0 watermark. */

	result->plane_res_b = res_blocks;

	result->plane_res_l = res_lines;