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Commit 8b2b53ce authored by Mahesh Kumar's avatar Mahesh Kumar Committed by Maarten Lankhorst
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drm/i915/skl+: make sure higher latency level has higher wm value 



DDB allocation optimization algorithm requires/assumes ddb allocation for
any memory C-state level DDB value to be as high as level below the
current level. Render decompression requires level WM to be as high as
wm level-0. This patch fulfils both the requirements.

v2: Changed plane_num to plane_id in skl_compute_wm_levels

v3: Addressed review comments from Shashank Sharma
Changed the commit message "statement can be more clear,
"DDB value to be as high as level below " what is level below ?"

v4: Added reviewed by tag from Shashank Sharma

v5: Added reviewed by from Juha-Pekka Heikkila

v6: Rebased the series

Reviewed-by: default avatarJuha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: default avatarShashank Sharma <shashank.sharma@intel.com>
Signed-off-by: default avatarMahesh Kumar <mahesh1.kumar@intel.com>
Reviewed-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1523245273-30264-8-git-send-email-vidya.srinivas@intel.com
parent 62027b77

drivers/gpu/drm/i915/intel_pm.c

+18 −0
Original line number Diff line number Diff line
@@ -4529,6 +4529,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, 
				uint16_t ddb_allocation,

				int level,

				const struct skl_wm_params *wp,

				const struct skl_wm_level *result_prev,

				struct skl_wm_level *result /* out */)

{

	const struct drm_plane_state *pstate = &intel_pstate->base;
@@ -4596,6 +4597,15 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, 
		} else {

			res_blocks++;

		}



		/*

		 * Make sure result blocks for higher latency levels are atleast

		 * as high as level below the current level.

		 * Assumption in DDB algorithm optimization for special cases.

		 * Also covers Display WA #1125 for RC.

		 */

		if (result_prev->plane_res_b > res_blocks)

			res_blocks = result_prev->plane_res_b;

	}



	if (INTEL_GEN(dev_priv) >= 11) {
@@ -4679,6 +4689,13 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv, 
	for (level = 0; level <= max_level; level++) {

		struct skl_wm_level *result = plane_id ? &wm->uv_wm[level] :

							  &wm->wm[level];

		struct skl_wm_level *result_prev;



		if (level)

			result_prev = plane_id ? &wm->uv_wm[level - 1] :

						  &wm->wm[level - 1];

		else

			result_prev = plane_id ? &wm->uv_wm[0] : &wm->wm[0];



		ret = skl_compute_plane_wm(dev_priv,

					   cstate,
@@ -4686,6 +4703,7 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv, 
					   ddb_blocks,

					   level,

					   wm_params,

					   result_prev,

					   result);

		if (ret)

			return ret;