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Commit 06a5687f authored by Mark Brown's avatar Mark Brown
Browse files

Merge remote-tracking branches 'spi/fix/dw', 'spi/fix/msiof' and 'spi/fix/pxa2xx' into spi-linus

parents ec6f34e5 3dbb3b98 6d40530e c957e8f0

drivers/spi/spi-dw-mid.c

+0 −1
Original line number Diff line number Diff line
@@ -271,7 +271,6 @@ int dw_spi_mid_init(struct dw_spi *dws) 
	iounmap(clk_reg);



	dws->num_cs = 16;

	dws->fifo_len = 40;	/* FIFO has 40 words buffer */



#ifdef CONFIG_SPI_DW_MID_DMA

	dws->dma_priv = kzalloc(sizeof(struct mid_dma), GFP_KERNEL);

drivers/spi/spi-dw.c

+3 −3
Original line number Diff line number Diff line
@@ -621,13 +621,13 @@ static void spi_hw_init(struct dw_spi *dws) 
	if (!dws->fifo_len) {

		u32 fifo;



		for (fifo = 2; fifo <= 257; fifo++) {

		for (fifo = 2; fifo <= 256; fifo++) {

			dw_writew(dws, DW_SPI_TXFLTR, fifo);

			if (fifo != dw_readw(dws, DW_SPI_TXFLTR))

				break;

		}



		dws->fifo_len = (fifo == 257) ? 0 : fifo;

		dws->fifo_len = (fifo == 2) ? 0 : fifo - 1;

		dw_writew(dws, DW_SPI_TXFLTR, 0);

	}

}
@@ -673,7 +673,7 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws) 
	if (dws->dma_ops && dws->dma_ops->dma_init) {

		ret = dws->dma_ops->dma_init(dws);

		if (ret) {

			dev_warn(&master->dev, "DMA init failed\n");

			dev_warn(dev, "DMA init failed\n");

			dws->dma_inited = 0;

		}

	}

drivers/spi/spi-pxa2xx.c

+1 −1
Original line number Diff line number Diff line
@@ -546,8 +546,8 @@ static void giveback(struct driver_data *drv_data) 
			cs_deassert(drv_data);

	}



	spi_finalize_current_message(drv_data->master);

	drv_data->cur_chip = NULL;

	spi_finalize_current_message(drv_data->master);

}



static void reset_sccr1(struct driver_data *drv_data)

drivers/spi/spi-sh-msiof.c

+1 −1
Original line number Diff line number Diff line
@@ -82,7 +82,7 @@ struct sh_msiof_spi_priv { 
#define MDR1_SYNCMD_LR	 0x30000000 /*   L/R mode */

#define MDR1_SYNCAC_SHIFT	 25 /* Sync Polarity (1 = Active-low) */

#define MDR1_BITLSB_SHIFT	 24 /* MSB/LSB First (1 = LSB first) */

#define MDR1_FLD_MASK	 0x000000c0 /* Frame Sync Signal Interval (0-3) */

#define MDR1_FLD_MASK	 0x0000000c /* Frame Sync Signal Interval (0-3) */

#define MDR1_FLD_SHIFT		  2

#define MDR1_XXSTP	 0x00000001 /* Transmission/Reception Stop on FIFO */

/* TMDR1 */