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Commit 6d40530e authored by Yoshihiro Shimoda's avatar Yoshihiro Shimoda Committed by Mark Brown
Browse files

spi: sh-msiof: fix MDR1_FLD_MASK value 



Since the FLD bit field is bit[3:2], the MDR1_FLD_MASK value should
be 0x0000000c.

Signed-off-by: default avatarYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 97bf6af1

drivers/spi/spi-sh-msiof.c

+1 −1
Original line number Diff line number Diff line
@@ -82,7 +82,7 @@ struct sh_msiof_spi_priv { 
#define MDR1_SYNCMD_LR	 0x30000000 /*   L/R mode */

#define MDR1_SYNCAC_SHIFT	 25 /* Sync Polarity (1 = Active-low) */

#define MDR1_BITLSB_SHIFT	 24 /* MSB/LSB First (1 = LSB first) */

#define MDR1_FLD_MASK	 0x000000c0 /* Frame Sync Signal Interval (0-3) */

#define MDR1_FLD_MASK	 0x0000000c /* Frame Sync Signal Interval (0-3) */

#define MDR1_FLD_SHIFT		  2

#define MDR1_XXSTP	 0x00000001 /* Transmission/Reception Stop on FIFO */

/* TMDR1 */