Loading msm/Makefile +1 −0 Original line number Diff line number Diff line Loading @@ -22,6 +22,7 @@ msm-vidc-objs := vidc/msm_v4l2_vidc.o \ vidc/hfi_packetization.o \ vidc/vidc_hfi.o \ vidc/msm_vidc_clocks.o \ vidc/msm_vidc_bus_ar50lite.o\ vidc/msm_vidc_bus_iris1.o \ vidc/msm_vidc_bus_iris2.o \ vidc/msm_vidc_buffer_calculations.o Loading msm/vidc/hfi_ar50_lt.c +40 −0 Original line number Diff line number Diff line Loading @@ -53,6 +53,7 @@ /* VIDC_UC_REGION_ADDR */ #define VIDC_CPU_CS_SCIBARG2_AR50_LT (VIDC_CPU_CS_BASE_OFFS_AR50_LT + 0x68) #define VIDC_CPU_IC_SOFTINT_EN_AR50_LT (VIDC_CPU_IC_BASE_OFFS_AR50_LT + 0x148) #define VIDC_CPU_IC_SOFTINT_AR50_LT (VIDC_CPU_IC_BASE_OFFS_AR50_LT + 0x150) #define VIDC_CPU_IC_SOFTINT_H2A_BMSK_AR50_LT 0x8000 #define VIDC_CPU_IC_SOFTINT_H2A_SHFT_AR50_LT 0x1 Loading Loading @@ -92,6 +93,15 @@ #define VIDC_WRAPPER_INTR_CLEAR_A2H_BMSK_AR50_LT 0x4 #define VIDC_WRAPPER_INTR_CLEAR_A2H_SHFT_AR50_LT 0x2 /* * -------------------------------------------------------------------------- * MODULE: tz_wrapper * -------------------------------------------------------------------------- */ #define VIDC_WRAPPER_TZ_BASE_OFFS 0x000C0000 #define VIDC_WRAPPER_TZ_CPU_CLOCK_CONFIG (VIDC_WRAPPER_TZ_BASE_OFFS) #define VIDC_WRAPPER_TZ_CPU_STATUS (VIDC_WRAPPER_TZ_BASE_OFFS + 0x10) #define VIDC_CTRL_INIT_AR50_LT VIDC_CPU_CS_SCIACMD_AR50_LT #define VIDC_CTRL_STATUS_AR50_LT VIDC_CPU_CS_SCIACMDARG0_AR50_LT Loading Loading @@ -156,6 +166,7 @@ int __prepare_pc_ar50_lt(struct venus_hfi_device *device) int rc = 0; u32 wfi_status = 0, idle_status = 0, pc_ready = 0; u32 ctrl_status = 0; u32 count = 0, max_tries = 10; ctrl_status = __read_register(device, VIDC_CTRL_STATUS_AR50_LT, DEFAULT_SID); pc_ready = ctrl_status & VIDC_CTRL_STATUS_PC_READY_AR50_LT; Loading @@ -165,11 +176,37 @@ int __prepare_pc_ar50_lt(struct venus_hfi_device *device) d_vpr_l("Already in pc_ready state\n"); return 0; } wfi_status = BIT(0) & __read_register(device, VIDC_WRAPPER_TZ_CPU_STATUS, DEFAULT_SID); if (!wfi_status || !idle_status) { d_vpr_e("Skipping PC, wfi status not set\n"); goto skip_power_off; } rc = __prepare_pc(device); if (rc) { d_vpr_e("Failed __prepare_pc %d\n", rc); goto skip_power_off; } while (count < max_tries) { wfi_status = BIT(0) & __read_register(device, VIDC_WRAPPER_TZ_CPU_STATUS, DEFAULT_SID); ctrl_status = __read_register(device, VIDC_CTRL_STATUS_AR50_LT, DEFAULT_SID); pc_ready = ctrl_status & VIDC_CTRL_STATUS_PC_READY_AR50_LT; if (wfi_status && pc_ready) break; usleep_range(150, 250); count++; } if (count == max_tries) { d_vpr_e("Skip PC. Core is not in right state\n"); goto skip_power_off; } return rc; skip_power_off: Loading Loading @@ -234,5 +271,8 @@ int __boot_firmware_ar50_lt(struct venus_hfi_device *device, u32 sid) s_vpr_e(sid, "Error booting up vidc firmware\n"); rc = -ETIME; } /* Enable interrupt before sending commands to venus */ __write_register(device, VIDC_CPU_IC_SOFTINT_EN_AR50_LT, 0x1, sid); return rc; } msm/vidc/hfi_iris1.c +1 −1 Original line number Diff line number Diff line Loading @@ -28,7 +28,7 @@ void __setup_ucregion_memory_map_iris1(struct venus_hfi_device *device, u32 sid) __write_register(device, QTBL_ADDR, (u32)device->iface_q_table.align_device_addr, sid); __write_register(device, QTBL_INFO, 0x01, sid); if (device->sfr.align_device_addr, sid) if (device->sfr.align_device_addr) __write_register(device, SFR_ADDR, (u32)device->sfr.align_device_addr, sid); if (device->qdss.align_device_addr) Loading msm/vidc/msm_vdec.c +2 −0 Original line number Diff line number Diff line Loading @@ -761,6 +761,7 @@ int msm_vdec_inst_init(struct msm_vidc_inst *inst) inst->prop.extradata_ctrls = EXTRADATA_DEFAULT; f = &inst->fmts[OUTPUT_PORT].v4l2_fmt; f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; f->fmt.pix_mp.height = DEFAULT_HEIGHT; f->fmt.pix_mp.width = DEFAULT_WIDTH; f->fmt.pix_mp.pixelformat = V4L2_PIX_FMT_NV12_UBWC; Loading @@ -782,6 +783,7 @@ int msm_vdec_inst_init(struct msm_vidc_inst *inst) strlcpy(inst->fmts[OUTPUT_PORT].description, fmt_desc->description, sizeof(inst->fmts[OUTPUT_PORT].description)); f = &inst->fmts[INPUT_PORT].v4l2_fmt; f->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; f->fmt.pix_mp.height = DEFAULT_HEIGHT; f->fmt.pix_mp.width = DEFAULT_WIDTH; f->fmt.pix_mp.pixelformat = V4L2_PIX_FMT_H264; Loading msm/vidc/msm_venc.c +13 −5 Original line number Diff line number Diff line Loading @@ -1138,6 +1138,7 @@ int msm_venc_inst_init(struct msm_vidc_inst *inst) return -EINVAL; } f = &inst->fmts[OUTPUT_PORT].v4l2_fmt; f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; f->fmt.pix_mp.height = DEFAULT_HEIGHT; f->fmt.pix_mp.width = DEFAULT_WIDTH; f->fmt.pix_mp.pixelformat = V4L2_PIX_FMT_H264; Loading @@ -1157,6 +1158,7 @@ int msm_venc_inst_init(struct msm_vidc_inst *inst) strlcpy(inst->fmts[OUTPUT_PORT].description, fmt_desc->description, sizeof(inst->fmts[OUTPUT_PORT].description)); f = &inst->fmts[INPUT_PORT].v4l2_fmt; f->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; f->fmt.pix_mp.height = DEFAULT_HEIGHT; f->fmt.pix_mp.width = DEFAULT_WIDTH; f->fmt.pix_mp.pixelformat = V4L2_PIX_FMT_NV12_UBWC; Loading Loading @@ -1679,6 +1681,12 @@ int msm_venc_s_ctrl(struct msm_vidc_inst *inst, struct v4l2_ctrl *ctrl) break; case V4L2_CID_MPEG_VIDC_VIDEO_OPERATING_RATE: inst->clk_data.operating_rate = ctrl->val; /* For HEIC image encode, set operating rate to 1 */ if (is_grid_session(inst)) { s_vpr_h(sid, "%s: set operating rate to 1 for HEIC\n", __func__); inst->clk_data.operating_rate = 1 << 16; } inst->flags &= ~VIDC_TURBO; if (ctrl->val == INT_MAX) inst->flags |= VIDC_TURBO; Loading Loading @@ -1918,6 +1926,9 @@ int msm_venc_s_ctrl(struct msm_vidc_inst *inst, struct v4l2_ctrl *ctrl) s_vpr_h(sid, "%s: set fps to 1 for HEIC\n", __func__); inst->clk_data.frame_rate = 1 << 16; s_vpr_h(sid, "%s: set operating rate to 1 for HEIC\n", __func__); inst->clk_data.operating_rate = 1 << 16; } break; case V4L2_CID_MPEG_VIDC_VIDEO_FULL_RANGE: Loading Loading @@ -2200,7 +2211,6 @@ int msm_venc_set_operating_rate(struct msm_vidc_inst *inst) { int rc = 0; struct hfi_device *hdev; struct v4l2_ctrl *ctrl; struct hfi_operating_rate op_rate; if (!inst || !inst->core) { Loading @@ -2211,9 +2221,7 @@ int msm_venc_set_operating_rate(struct msm_vidc_inst *inst) return 0; hdev = inst->core->device; ctrl = get_ctrl(inst, V4L2_CID_MPEG_VIDC_VIDEO_OPERATING_RATE); op_rate.operating_rate = ctrl->val; op_rate.operating_rate = inst->clk_data.operating_rate; s_vpr_h(inst->sid, "%s: %d\n", __func__, op_rate.operating_rate >> 16); rc = call_hfi_op(hdev, session_set_property, inst->session, Loading Loading @@ -2607,7 +2615,7 @@ int msm_venc_set_vbv_delay(struct msm_vidc_inst *inst) } hdev = inst->core->device; f = &inst->fmts[INPUT_PORT].v4l2_fmt; f = &inst->fmts[OUTPUT_PORT].v4l2_fmt; codec = get_v4l2_codec(inst); height = f->fmt.pix_mp.height; width = f->fmt.pix_mp.width; Loading Loading
msm/Makefile +1 −0 Original line number Diff line number Diff line Loading @@ -22,6 +22,7 @@ msm-vidc-objs := vidc/msm_v4l2_vidc.o \ vidc/hfi_packetization.o \ vidc/vidc_hfi.o \ vidc/msm_vidc_clocks.o \ vidc/msm_vidc_bus_ar50lite.o\ vidc/msm_vidc_bus_iris1.o \ vidc/msm_vidc_bus_iris2.o \ vidc/msm_vidc_buffer_calculations.o Loading
msm/vidc/hfi_ar50_lt.c +40 −0 Original line number Diff line number Diff line Loading @@ -53,6 +53,7 @@ /* VIDC_UC_REGION_ADDR */ #define VIDC_CPU_CS_SCIBARG2_AR50_LT (VIDC_CPU_CS_BASE_OFFS_AR50_LT + 0x68) #define VIDC_CPU_IC_SOFTINT_EN_AR50_LT (VIDC_CPU_IC_BASE_OFFS_AR50_LT + 0x148) #define VIDC_CPU_IC_SOFTINT_AR50_LT (VIDC_CPU_IC_BASE_OFFS_AR50_LT + 0x150) #define VIDC_CPU_IC_SOFTINT_H2A_BMSK_AR50_LT 0x8000 #define VIDC_CPU_IC_SOFTINT_H2A_SHFT_AR50_LT 0x1 Loading Loading @@ -92,6 +93,15 @@ #define VIDC_WRAPPER_INTR_CLEAR_A2H_BMSK_AR50_LT 0x4 #define VIDC_WRAPPER_INTR_CLEAR_A2H_SHFT_AR50_LT 0x2 /* * -------------------------------------------------------------------------- * MODULE: tz_wrapper * -------------------------------------------------------------------------- */ #define VIDC_WRAPPER_TZ_BASE_OFFS 0x000C0000 #define VIDC_WRAPPER_TZ_CPU_CLOCK_CONFIG (VIDC_WRAPPER_TZ_BASE_OFFS) #define VIDC_WRAPPER_TZ_CPU_STATUS (VIDC_WRAPPER_TZ_BASE_OFFS + 0x10) #define VIDC_CTRL_INIT_AR50_LT VIDC_CPU_CS_SCIACMD_AR50_LT #define VIDC_CTRL_STATUS_AR50_LT VIDC_CPU_CS_SCIACMDARG0_AR50_LT Loading Loading @@ -156,6 +166,7 @@ int __prepare_pc_ar50_lt(struct venus_hfi_device *device) int rc = 0; u32 wfi_status = 0, idle_status = 0, pc_ready = 0; u32 ctrl_status = 0; u32 count = 0, max_tries = 10; ctrl_status = __read_register(device, VIDC_CTRL_STATUS_AR50_LT, DEFAULT_SID); pc_ready = ctrl_status & VIDC_CTRL_STATUS_PC_READY_AR50_LT; Loading @@ -165,11 +176,37 @@ int __prepare_pc_ar50_lt(struct venus_hfi_device *device) d_vpr_l("Already in pc_ready state\n"); return 0; } wfi_status = BIT(0) & __read_register(device, VIDC_WRAPPER_TZ_CPU_STATUS, DEFAULT_SID); if (!wfi_status || !idle_status) { d_vpr_e("Skipping PC, wfi status not set\n"); goto skip_power_off; } rc = __prepare_pc(device); if (rc) { d_vpr_e("Failed __prepare_pc %d\n", rc); goto skip_power_off; } while (count < max_tries) { wfi_status = BIT(0) & __read_register(device, VIDC_WRAPPER_TZ_CPU_STATUS, DEFAULT_SID); ctrl_status = __read_register(device, VIDC_CTRL_STATUS_AR50_LT, DEFAULT_SID); pc_ready = ctrl_status & VIDC_CTRL_STATUS_PC_READY_AR50_LT; if (wfi_status && pc_ready) break; usleep_range(150, 250); count++; } if (count == max_tries) { d_vpr_e("Skip PC. Core is not in right state\n"); goto skip_power_off; } return rc; skip_power_off: Loading Loading @@ -234,5 +271,8 @@ int __boot_firmware_ar50_lt(struct venus_hfi_device *device, u32 sid) s_vpr_e(sid, "Error booting up vidc firmware\n"); rc = -ETIME; } /* Enable interrupt before sending commands to venus */ __write_register(device, VIDC_CPU_IC_SOFTINT_EN_AR50_LT, 0x1, sid); return rc; }
msm/vidc/hfi_iris1.c +1 −1 Original line number Diff line number Diff line Loading @@ -28,7 +28,7 @@ void __setup_ucregion_memory_map_iris1(struct venus_hfi_device *device, u32 sid) __write_register(device, QTBL_ADDR, (u32)device->iface_q_table.align_device_addr, sid); __write_register(device, QTBL_INFO, 0x01, sid); if (device->sfr.align_device_addr, sid) if (device->sfr.align_device_addr) __write_register(device, SFR_ADDR, (u32)device->sfr.align_device_addr, sid); if (device->qdss.align_device_addr) Loading
msm/vidc/msm_vdec.c +2 −0 Original line number Diff line number Diff line Loading @@ -761,6 +761,7 @@ int msm_vdec_inst_init(struct msm_vidc_inst *inst) inst->prop.extradata_ctrls = EXTRADATA_DEFAULT; f = &inst->fmts[OUTPUT_PORT].v4l2_fmt; f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; f->fmt.pix_mp.height = DEFAULT_HEIGHT; f->fmt.pix_mp.width = DEFAULT_WIDTH; f->fmt.pix_mp.pixelformat = V4L2_PIX_FMT_NV12_UBWC; Loading @@ -782,6 +783,7 @@ int msm_vdec_inst_init(struct msm_vidc_inst *inst) strlcpy(inst->fmts[OUTPUT_PORT].description, fmt_desc->description, sizeof(inst->fmts[OUTPUT_PORT].description)); f = &inst->fmts[INPUT_PORT].v4l2_fmt; f->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; f->fmt.pix_mp.height = DEFAULT_HEIGHT; f->fmt.pix_mp.width = DEFAULT_WIDTH; f->fmt.pix_mp.pixelformat = V4L2_PIX_FMT_H264; Loading
msm/vidc/msm_venc.c +13 −5 Original line number Diff line number Diff line Loading @@ -1138,6 +1138,7 @@ int msm_venc_inst_init(struct msm_vidc_inst *inst) return -EINVAL; } f = &inst->fmts[OUTPUT_PORT].v4l2_fmt; f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; f->fmt.pix_mp.height = DEFAULT_HEIGHT; f->fmt.pix_mp.width = DEFAULT_WIDTH; f->fmt.pix_mp.pixelformat = V4L2_PIX_FMT_H264; Loading @@ -1157,6 +1158,7 @@ int msm_venc_inst_init(struct msm_vidc_inst *inst) strlcpy(inst->fmts[OUTPUT_PORT].description, fmt_desc->description, sizeof(inst->fmts[OUTPUT_PORT].description)); f = &inst->fmts[INPUT_PORT].v4l2_fmt; f->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; f->fmt.pix_mp.height = DEFAULT_HEIGHT; f->fmt.pix_mp.width = DEFAULT_WIDTH; f->fmt.pix_mp.pixelformat = V4L2_PIX_FMT_NV12_UBWC; Loading Loading @@ -1679,6 +1681,12 @@ int msm_venc_s_ctrl(struct msm_vidc_inst *inst, struct v4l2_ctrl *ctrl) break; case V4L2_CID_MPEG_VIDC_VIDEO_OPERATING_RATE: inst->clk_data.operating_rate = ctrl->val; /* For HEIC image encode, set operating rate to 1 */ if (is_grid_session(inst)) { s_vpr_h(sid, "%s: set operating rate to 1 for HEIC\n", __func__); inst->clk_data.operating_rate = 1 << 16; } inst->flags &= ~VIDC_TURBO; if (ctrl->val == INT_MAX) inst->flags |= VIDC_TURBO; Loading Loading @@ -1918,6 +1926,9 @@ int msm_venc_s_ctrl(struct msm_vidc_inst *inst, struct v4l2_ctrl *ctrl) s_vpr_h(sid, "%s: set fps to 1 for HEIC\n", __func__); inst->clk_data.frame_rate = 1 << 16; s_vpr_h(sid, "%s: set operating rate to 1 for HEIC\n", __func__); inst->clk_data.operating_rate = 1 << 16; } break; case V4L2_CID_MPEG_VIDC_VIDEO_FULL_RANGE: Loading Loading @@ -2200,7 +2211,6 @@ int msm_venc_set_operating_rate(struct msm_vidc_inst *inst) { int rc = 0; struct hfi_device *hdev; struct v4l2_ctrl *ctrl; struct hfi_operating_rate op_rate; if (!inst || !inst->core) { Loading @@ -2211,9 +2221,7 @@ int msm_venc_set_operating_rate(struct msm_vidc_inst *inst) return 0; hdev = inst->core->device; ctrl = get_ctrl(inst, V4L2_CID_MPEG_VIDC_VIDEO_OPERATING_RATE); op_rate.operating_rate = ctrl->val; op_rate.operating_rate = inst->clk_data.operating_rate; s_vpr_h(inst->sid, "%s: %d\n", __func__, op_rate.operating_rate >> 16); rc = call_hfi_op(hdev, session_set_property, inst->session, Loading Loading @@ -2607,7 +2615,7 @@ int msm_venc_set_vbv_delay(struct msm_vidc_inst *inst) } hdev = inst->core->device; f = &inst->fmts[INPUT_PORT].v4l2_fmt; f = &inst->fmts[OUTPUT_PORT].v4l2_fmt; codec = get_v4l2_codec(inst); height = f->fmt.pix_mp.height; width = f->fmt.pix_mp.width; Loading