Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 03dca708 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2014-11-07' of git://anongit.freedesktop.org/drm-intel into drm-fixes 

Black screen, screen corruption, hardware state corruption fixes.

* tag 'drm-intel-fixes-2014-11-07' of git://anongit.freedesktop.org/drm-intel:
  drm/i915: safeguard against too high minimum brightness
  drm/i915: vlv: fix gunit HW state corruption during S4 suspend
  drm/i915: Disable caches for Global GTT.
parents 2730fa0d e1c412e7

drivers/gpu/drm/i915/i915_drv.c

+10 −0
Original line number Diff line number Diff line
@@ -986,6 +986,15 @@ static int i915_pm_freeze(struct device *dev) 
	return i915_drm_freeze(drm_dev);

}



static int i915_pm_freeze_late(struct device *dev)

{

	struct pci_dev *pdev = to_pci_dev(dev);

	struct drm_device *drm_dev = pci_get_drvdata(pdev);

	struct drm_i915_private *dev_priv = drm_dev->dev_private;



	return intel_suspend_complete(dev_priv);

}



static int i915_pm_thaw_early(struct device *dev)

{

	struct pci_dev *pdev = to_pci_dev(dev);
@@ -1570,6 +1579,7 @@ static const struct dev_pm_ops i915_pm_ops = { 
	.resume_early = i915_pm_resume_early,

	.resume = i915_pm_resume,

	.freeze = i915_pm_freeze,

	.freeze_late = i915_pm_freeze_late,

	.thaw_early = i915_pm_thaw_early,

	.thaw = i915_pm_thaw,

	.poweroff = i915_pm_poweroff,

drivers/gpu/drm/i915/i915_gem_gtt.c

+16 −0
Original line number Diff line number Diff line
@@ -1902,6 +1902,22 @@ static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv) 
	      GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |

	      GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));



	if (!USES_PPGTT(dev_priv->dev))

		/* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,

		 * so RTL will always use the value corresponding to

		 * pat_sel = 000".

		 * So let's disable cache for GGTT to avoid screen corruptions.

		 * MOCS still can be used though.

		 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work

		 * before this patch, i.e. the same uncached + snooping access

		 * like on gen6/7 seems to be in effect.

		 * - So this just fixes blitter/render access. Again it looks

		 * like it's not just uncached access, but uncached + snooping.

		 * So we can still hold onto all our assumptions wrt cpu

		 * clflushing on LLC machines.

		 */

		pat = GEN8_PPAT(0, GEN8_PPAT_UC);



	/* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b

	 * write would work. */

	I915_WRITE(GEN8_PRIVATE_PAT, pat);

drivers/gpu/drm/i915/intel_panel.c

+15 −2
Original line number Diff line number Diff line
@@ -1098,12 +1098,25 @@ static u32 get_backlight_min_vbt(struct intel_connector *connector) 
	struct drm_device *dev = connector->base.dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_panel *panel = &connector->panel;

	int min;



	WARN_ON(panel->backlight.max == 0);



	/*

	 * XXX: If the vbt value is 255, it makes min equal to max, which leads

	 * to problems. There are such machines out there. Either our

	 * interpretation is wrong or the vbt has bogus data. Or both. Safeguard

	 * against this by letting the minimum be at most (arbitrarily chosen)

	 * 25% of the max.

	 */

	min = clamp_t(int, dev_priv->vbt.backlight.min_brightness, 0, 64);

	if (min != dev_priv->vbt.backlight.min_brightness) {

		DRM_DEBUG_KMS("clamping VBT min backlight %d/255 to %d/255\n",

			      dev_priv->vbt.backlight.min_brightness, min);

	}



	/* vbt value is a coefficient in range [0..255] */

	return scale(dev_priv->vbt.backlight.min_brightness, 0, 255,

		     0, panel->backlight.max);

	return scale(min, 0, 255, 0, panel->backlight.max);

}



static int bdw_setup_backlight(struct intel_connector *connector)