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Commit 0270be3e authored by Thomas Gleixner's avatar Thomas Gleixner
Browse files

x86/speculation: Rework speculative_store_bypass_update() 



The upcoming support for the virtual SPEC_CTRL MSR on AMD needs to reuse
speculative_store_bypass_update() to avoid code duplication. Add an
argument for supplying a thread info (TIF) value and create a wrapper
speculative_store_bypass_update_current() which is used at the existing
call site.

Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Reviewed-by: default avatarBorislav Petkov <bp@suse.de>
Reviewed-by: default avatarKonrad Rzeszutek Wilk <konrad.wilk@oracle.com>
parent 11fb0683

arch/x86/include/asm/spec-ctrl.h

+6 −1
Original line number Diff line number Diff line
@@ -42,6 +42,11 @@ extern void speculative_store_bypass_ht_init(void); 
static inline void speculative_store_bypass_ht_init(void) { }

#endif



extern void speculative_store_bypass_update(void);

extern void speculative_store_bypass_update(unsigned long tif);



static inline void speculative_store_bypass_update_current(void)

{

	speculative_store_bypass_update(current_thread_info()->flags);

}



#endif

arch/x86/kernel/cpu/bugs.c

+1 −1
Original line number Diff line number Diff line
@@ -598,7 +598,7 @@ static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl) 
	 * mitigation until it is next scheduled.

	 */

	if (task == current && update)

		speculative_store_bypass_update();

		speculative_store_bypass_update_current();



	return 0;

}

arch/x86/kernel/process.c

+2 −2
Original line number Diff line number Diff line
@@ -414,10 +414,10 @@ static __always_inline void __speculative_store_bypass_update(unsigned long tifn 
		intel_set_ssb_state(tifn);

}



void speculative_store_bypass_update(void)

void speculative_store_bypass_update(unsigned long tif)

{

	preempt_disable();

	__speculative_store_bypass_update(current_thread_info()->flags);

	__speculative_store_bypass_update(tif);

	preempt_enable();

}