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Commit 11fb0683 authored by Tom Lendacky's avatar Tom Lendacky Committed by Thomas Gleixner
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x86/speculation: Add virtualized speculative store bypass disable support 



Some AMD processors only support a non-architectural means of enabling
speculative store bypass disable (SSBD).  To allow a simplified view of
this to a guest, an architectural definition has been created through a new
CPUID bit, 0x80000008_EBX[25], and a new MSR, 0xc001011f.  With this, a
hypervisor can virtualize the existence of this definition and provide an
architectural method for using SSBD to a guest.

Add the new CPUID feature, the new MSR and update the existing SSBD
support to use this MSR when present.

Signed-off-by: default avatarTom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Reviewed-by: default avatarBorislav Petkov <bp@suse.de>
parent ccbcd267

arch/x86/include/asm/cpufeatures.h

+1 −0
Original line number Diff line number Diff line
@@ -282,6 +282,7 @@ 
#define X86_FEATURE_AMD_IBPB		(13*32+12) /* "" Indirect Branch Prediction Barrier */

#define X86_FEATURE_AMD_IBRS		(13*32+14) /* "" Indirect Branch Restricted Speculation */

#define X86_FEATURE_AMD_STIBP		(13*32+15) /* "" Single Thread Indirect Branch Predictors */

#define X86_FEATURE_VIRT_SSBD		(13*32+25) /* Virtualized Speculative Store Bypass Disable */



/* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */

#define X86_FEATURE_DTHERM		(14*32+ 0) /* Digital Thermal Sensor */

arch/x86/include/asm/msr-index.h

+2 −0
Original line number Diff line number Diff line
@@ -347,6 +347,8 @@ 
#define MSR_AMD64_SEV_ENABLED_BIT	0

#define MSR_AMD64_SEV_ENABLED		BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT)



#define MSR_AMD64_VIRT_SPEC_CTRL	0xc001011f



/* Fam 17h MSRs */

#define MSR_F17H_IRPERF			0xc00000e9

arch/x86/kernel/cpu/bugs.c

+3 −1
Original line number Diff line number Diff line
@@ -205,7 +205,9 @@ static void x86_amd_ssb_disable(void) 
{

	u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask;



	if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))

	if (boot_cpu_has(X86_FEATURE_VIRT_SSBD))

		wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD);

	else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))

		wrmsrl(MSR_AMD64_LS_CFG, msrval);

}

arch/x86/kernel/process.c

+12 −1
Original line number Diff line number Diff line
@@ -388,6 +388,15 @@ static __always_inline void amd_set_core_ssb_state(unsigned long tifn) 
}

#endif



static __always_inline void amd_set_ssb_virt_state(unsigned long tifn)

{

	/*

	 * SSBD has the same definition in SPEC_CTRL and VIRT_SPEC_CTRL,

	 * so ssbd_tif_to_spec_ctrl() just works.

	 */

	wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn));

}



static __always_inline void intel_set_ssb_state(unsigned long tifn)

{

	u64 msr = x86_spec_ctrl_base | ssbd_tif_to_spec_ctrl(tifn);
@@ -397,7 +406,9 @@ static __always_inline void intel_set_ssb_state(unsigned long tifn) 


static __always_inline void __speculative_store_bypass_update(unsigned long tifn)

{

	if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD))

	if (static_cpu_has(X86_FEATURE_VIRT_SSBD))

		amd_set_ssb_virt_state(tifn);

	else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD))

		amd_set_core_ssb_state(tifn);

	else

		intel_set_ssb_state(tifn);