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Commit fef3a7a1 authored by Huang Ying's avatar Huang Ying Committed by H. Peter Anvin
Browse files

x86, kexec: fix kexec x86 coding style 



Impact: Cleanup

Fix some coding style issue for kexec x86.

Signed-off-by: default avatarHuang Ying <ying.huang@intel.com>
Signed-off-by: default avatarH. Peter Anvin <hpa@zytor.com>
parent 467c88fe

arch/x86/kernel/machine_kexec_32.c

+10 −7
Original line number Diff line number Diff line
@@ -14,12 +14,12 @@ 
#include <linux/ftrace.h>

#include <linux/suspend.h>

#include <linux/gfp.h>

#include <linux/io.h>



#include <asm/pgtable.h>

#include <asm/pgalloc.h>

#include <asm/tlbflush.h>

#include <asm/mmu_context.h>

#include <asm/io.h>

#include <asm/apic.h>

#include <asm/cpufeature.h>

#include <asm/desc.h>
@@ -205,7 +205,8 @@ void machine_kexec(struct kimage *image) 


	if (image->preserve_context) {

#ifdef CONFIG_X86_IO_APIC

		/* We need to put APICs in legacy mode so that we can

		/*

		 * We need to put APICs in legacy mode so that we can

		 * get timer interrupts in second kernel. kexec/kdump

		 * paths already have calls to disable_IO_APIC() in

		 * one form or other. kexec jump path also need
@@ -227,7 +228,8 @@ void machine_kexec(struct kimage *image) 
		page_list[PA_SWAP_PAGE] = (page_to_pfn(image->swap_page)

						<< PAGE_SHIFT);



	/* The segment registers are funny things, they have both a

	/*

	 * The segment registers are funny things, they have both a

	 * visible and an invisible part.  Whenever the visible part is

	 * set to a specific selector, the invisible part is loaded

	 * with from a table in memory.  At no other time is the
@@ -237,7 +239,8 @@ void machine_kexec(struct kimage *image) 
	 * segments, before I zap the gdt with an invalid value.

	 */

	load_segments();

	/* The gdt & idt are now invalid.

	/*

	 * The gdt & idt are now invalid.

	 * If you want to load them you must set up your own idt & gdt.

	 */

	set_gdt(phys_to_virt(0), 0);

arch/x86/kernel/machine_kexec_64.c

+8 −7
Original line number Diff line number Diff line
@@ -12,11 +12,11 @@ 
#include <linux/reboot.h>

#include <linux/numa.h>

#include <linux/ftrace.h>

#include <linux/io.h>



#include <asm/pgtable.h>

#include <asm/tlbflush.h>

#include <asm/mmu_context.h>

#include <asm/io.h>



static void init_level2_page(pmd_t *level2p, unsigned long addr)

{
@@ -83,9 +83,8 @@ static int init_level4_page(struct kimage *image, pgd_t *level4p, 
		}

		level3p = (pud_t *)page_address(page);

		result = init_level3_page(image, level3p, addr, last_addr);

		if (result) {

		if (result)

			goto out;

		}

		set_pgd(level4p++, __pgd(__pa(level3p) | _KERNPG_TABLE));

		addr += PGDIR_SIZE;

	}
@@ -242,7 +241,8 @@ void machine_kexec(struct kimage *image) 
	page_list[PA_TABLE_PAGE] =

	  (unsigned long)__pa(page_address(image->control_code_page));



	/* The segment registers are funny things, they have both a

	/*

	 * The segment registers are funny things, they have both a

	 * visible and an invisible part.  Whenever the visible part is

	 * set to a specific selector, the invisible part is loaded

	 * with from a table in memory.  At no other time is the
@@ -252,7 +252,8 @@ void machine_kexec(struct kimage *image) 
	 * segments, before I zap the gdt with an invalid value.

	 */

	load_segments();

	/* The gdt & idt are now invalid.

	/*

	 * The gdt & idt are now invalid.

	 * If you want to load them you must set up your own idt & gdt.

	 */

	set_gdt(phys_to_virt(0), 0);

arch/x86/kernel/relocate_kernel_32.S

+16 −8
Original line number Diff line number Diff line
@@ -17,7 +17,8 @@ 


#define PTR(x) (x << 2)



/* control_page + KEXEC_CONTROL_CODE_MAX_SIZE

/*

 * control_page + KEXEC_CONTROL_CODE_MAX_SIZE

 * ~ control_page + PAGE_SIZE are used as data storage and stack for

 * jumping back

 */
@@ -76,8 +77,10 @@ relocate_kernel: 
	movl	%eax, CP_PA_SWAP_PAGE(%edi)

	movl	%ebx, CP_PA_BACKUP_PAGES_MAP(%edi)



	/* get physical address of control page now */

	/* this is impossible after page table switch */

	/*

	 * get physical address of control page now

	 * this is impossible after page table switch

	 */

	movl	PTR(PA_CONTROL_PAGE)(%ebp), %edi



	/* switch to new set of page tables */
@@ -97,7 +100,8 @@ identity_mapped: 
	/* store the start address on the stack */

	pushl   %edx



	/* Set cr0 to a known state:

	/*

	 * Set cr0 to a known state:

	 *  - Paging disabled

	 *  - Alignment check disabled

	 *  - Write protect disabled
@@ -113,7 +117,8 @@ identity_mapped: 
	/* clear cr4 if applicable */

	testl	%ecx, %ecx

	jz	1f

	/* Set cr4 to a known state:

	/*

	 * Set cr4 to a known state:

	 * Setting everything to zero seems safe.

	 */

	xorl	%eax, %eax
@@ -132,15 +137,18 @@ identity_mapped: 
	call	swap_pages

	addl	$8, %esp



	/* To be certain of avoiding problems with self-modifying code

	/*

	 * To be certain of avoiding problems with self-modifying code

	 * I need to execute a serializing instruction here.

	 * So I flush the TLB, it's handy, and not processor dependent.

	 */

	xorl	%eax, %eax

	movl	%eax, %cr3



	/* set all of the registers to known values */

	/* leave %esp alone */

	/*

	 * set all of the registers to known values

	 * leave %esp alone

	 */



	testl	%esi, %esi

	jnz 1f

arch/x86/kernel/relocate_kernel_64.S

+16 −8
Original line number Diff line number Diff line
@@ -24,7 +24,8 @@ 
	.code64

	.globl relocate_kernel

relocate_kernel:

	/* %rdi indirection_page

	/*

	 * %rdi indirection_page

	 * %rsi page_list

	 * %rdx start address

	 */
@@ -33,8 +34,10 @@ relocate_kernel: 
	pushq $0

	popfq



	/* get physical address of control page now */

	/* this is impossible after page table switch */

	/*

	 * get physical address of control page now

	 * this is impossible after page table switch

	 */

	movq	PTR(PA_CONTROL_PAGE)(%rsi), %r8



	/* get physical address of page table now too */
@@ -55,7 +58,8 @@ identity_mapped: 
	/* store the start address on the stack */

	pushq   %rdx



	/* Set cr0 to a known state:

	/*

	 * Set cr0 to a known state:

	 *  - Paging enabled

	 *  - Alignment check disabled

	 *  - Write protect disabled
@@ -68,7 +72,8 @@ identity_mapped: 
	orl	$(X86_CR0_PG | X86_CR0_PE), %eax

	movq	%rax, %cr0



	/* Set cr4 to a known state:

	/*

	 * Set cr4 to a known state:

	 *  - physical address extension enabled

	 */

	movq	$X86_CR4_PAE, %rax
@@ -117,7 +122,8 @@ identity_mapped: 
	jmp	0b

3:



	/* To be certain of avoiding problems with self-modifying code

	/*

	 * To be certain of avoiding problems with self-modifying code

	 * I need to execute a serializing instruction here.

	 * So I flush the TLB by reloading %cr3 here, it's handy,

	 * and not processor dependent.
@@ -125,8 +131,10 @@ identity_mapped: 
	movq	%cr3, %rax

	movq	%rax, %cr3



	/* set all of the registers to known values */

	/* leave %rsp alone */

	/*

	 * set all of the registers to known values

	 * leave %rsp alone

	 */



	xorq	%rax, %rax

	xorq	%rbx, %rbx