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Commit fe79f1cf authored by Jordan Crouse's avatar Jordan Crouse Committed by Greg Kroah-Hartman
Browse files

drm/msm: Disable the RPTR shadow 



[ Upstream commit f6828e0c4045f03f9cf2df6c2a768102641183f4 ]

Disable the RPTR shadow across all targets. It will be selectively
re-enabled later for targets that need it.

Cc: stable@vger.kernel.org
Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 8cbe9b76

drivers/gpu/drm/msm/adreno/a2xx_gpu.c

+5 −0
Original line number Diff line number Diff line
@@ -164,6 +164,11 @@ static int a2xx_hw_init(struct msm_gpu *gpu) 
	if (ret)

		return ret;



	gpu_write(gpu, REG_AXXX_CP_RB_CNTL,

		MSM_GPU_RB_CNTL_DEFAULT | AXXX_CP_RB_CNTL_NO_UPDATE);



	gpu_write(gpu, REG_AXXX_CP_RB_BASE, lower_32_bits(gpu->rb[0]->iova));



	/* NOTE: PM4/micro-engine firmware registers look to be the same

	 * for a2xx and a3xx.. we could possibly push that part down to

	 * adreno_gpu base class.  Or push both PM4 and PFP but

drivers/gpu/drm/msm/adreno/a3xx_gpu.c

+10 −0
Original line number Diff line number Diff line
@@ -215,6 +215,16 @@ static int a3xx_hw_init(struct msm_gpu *gpu) 
	if (ret)

		return ret;



	/*

	 * Use the default ringbuffer size and block size but disable the RPTR

	 * shadow

	 */

	gpu_write(gpu, REG_AXXX_CP_RB_CNTL,

		MSM_GPU_RB_CNTL_DEFAULT | AXXX_CP_RB_CNTL_NO_UPDATE);



	/* Set the ringbuffer address */

	gpu_write(gpu, REG_AXXX_CP_RB_BASE, lower_32_bits(gpu->rb[0]->iova));



	/* setup access protection: */

	gpu_write(gpu, REG_A3XX_CP_PROTECT_CTRL, 0x00000007);

drivers/gpu/drm/msm/adreno/a4xx_gpu.c

+10 −0
Original line number Diff line number Diff line
@@ -265,6 +265,16 @@ static int a4xx_hw_init(struct msm_gpu *gpu) 
	if (ret)

		return ret;



	/*

	 * Use the default ringbuffer size and block size but disable the RPTR

	 * shadow

	 */

	gpu_write(gpu, REG_A4XX_CP_RB_CNTL,

		MSM_GPU_RB_CNTL_DEFAULT | AXXX_CP_RB_CNTL_NO_UPDATE);



	/* Set the ringbuffer address */

	gpu_write(gpu, REG_A4XX_CP_RB_BASE, lower_32_bits(gpu->rb[0]->iova));



	/* Load PM4: */

	ptr = (uint32_t *)(adreno_gpu->fw[ADRENO_FW_PM4]->data);

	len = adreno_gpu->fw[ADRENO_FW_PM4]->size / 4;

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

+9 −2
Original line number Diff line number Diff line
@@ -677,14 +677,21 @@ static int a5xx_hw_init(struct msm_gpu *gpu) 
	if (ret)

		return ret;



	a5xx_preempt_hw_init(gpu);



	a5xx_gpmu_ucode_init(gpu);



	ret = a5xx_ucode_init(gpu);

	if (ret)

		return ret;



	/* Set the ringbuffer address */

	gpu_write64(gpu, REG_A5XX_CP_RB_BASE, REG_A5XX_CP_RB_BASE_HI,

		gpu->rb[0]->iova);



	gpu_write(gpu, REG_A5XX_CP_RB_CNTL,

		MSM_GPU_RB_CNTL_DEFAULT | AXXX_CP_RB_CNTL_NO_UPDATE);



	a5xx_preempt_hw_init(gpu);



	/* Disable the interrupts through the initial bringup stage */

	gpu_write(gpu, REG_A5XX_RBBM_INT_0_MASK, A5XX_INT_MASK);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

+7 −0
Original line number Diff line number Diff line
@@ -512,6 +512,13 @@ static int a6xx_hw_init(struct msm_gpu *gpu) 
	if (ret)

		goto out;



	/* Set the ringbuffer address */

	gpu_write64(gpu, REG_A6XX_CP_RB_BASE, REG_A6XX_CP_RB_BASE_HI,

		gpu->rb[0]->iova);



	gpu_write(gpu, REG_A6XX_CP_RB_CNTL,

		MSM_GPU_RB_CNTL_DEFAULT | AXXX_CP_RB_CNTL_NO_UPDATE);



	/* Always come up on rb 0 */

	a6xx_gpu->cur_ring = gpu->rb[0];