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Commit fdb81fd7 authored by Likun Gao's avatar Likun Gao Committed by Alex Deucher
Browse files

drm/amdgpu: unify rlc function into structure 



Put function rlc_init,rlc_fini,rlc_resume,rlc_stop,rlc_start into structure
amdgpu_rlc_funcs and change the method to call rlc function for each verssion of
GFX.

Signed-off-by: default avatarLikun Gao <Likun.Gao@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a82c1566

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h

+6 −0
Original line number Diff line number Diff line
@@ -41,6 +41,12 @@ 
struct amdgpu_rlc_funcs {

	void (*enter_safe_mode)(struct amdgpu_device *adev);

	void (*exit_safe_mode)(struct amdgpu_device *adev);

	int  (*init)(struct amdgpu_device *adev);

	void (*fini)(struct amdgpu_device *adev);

	int  (*resume)(struct amdgpu_device *adev);

	void (*stop)(struct amdgpu_device *adev);

	void (*reset)(struct amdgpu_device *adev);

	void (*start)(struct amdgpu_device *adev);

};



struct amdgpu_rlc {

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

+19 −9
Original line number Diff line number Diff line
@@ -2386,7 +2386,7 @@ static int gfx_v6_0_rlc_init(struct amdgpu_device *adev) 
		if (r) {

			dev_warn(adev->dev, "(%d) create RLC sr bo failed\n",

				 r);

			gfx_v6_0_rlc_fini(adev);

			adev->gfx.rlc.funcs->fini(adev);

			return r;

		}
@@ -2411,7 +2411,7 @@ static int gfx_v6_0_rlc_init(struct amdgpu_device *adev) 
					      (void **)&adev->gfx.rlc.cs_ptr);

		if (r) {

			dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);

			gfx_v6_0_rlc_fini(adev);

			adev->gfx.rlc.funcs->fini(adev);

			return r;

		}
@@ -2532,8 +2532,8 @@ static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev) 
	if (!adev->gfx.rlc_fw)

		return -EINVAL;



	gfx_v6_0_rlc_stop(adev);

	gfx_v6_0_rlc_reset(adev);

	adev->gfx.rlc.funcs->stop(adev);

	adev->gfx.rlc.funcs->reset(adev);

	gfx_v6_0_init_pg(adev);

	gfx_v6_0_init_cg(adev);
@@ -2561,7 +2561,7 @@ static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev) 
	WREG32(mmRLC_UCODE_ADDR, 0);



	gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev));

	gfx_v6_0_rlc_start(adev);

	adev->gfx.rlc.funcs->start(adev);



	return 0;

}
@@ -3058,6 +3058,15 @@ static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = { 
	.select_me_pipe_q = &gfx_v6_0_select_me_pipe_q

};



static const struct amdgpu_rlc_funcs gfx_v6_0_rlc_funcs = {

	.init = gfx_v6_0_rlc_init,

	.fini = gfx_v6_0_rlc_fini,

	.resume = gfx_v6_0_rlc_resume,

	.stop = gfx_v6_0_rlc_stop,

	.reset = gfx_v6_0_rlc_reset,

	.start = gfx_v6_0_rlc_start

};



static int gfx_v6_0_early_init(void *handle)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -3065,6 +3074,7 @@ static int gfx_v6_0_early_init(void *handle) 
	adev->gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS;

	adev->gfx.num_compute_rings = GFX6_NUM_COMPUTE_RINGS;

	adev->gfx.funcs = &gfx_v6_0_gfx_funcs;

	adev->gfx.rlc.funcs = &gfx_v6_0_rlc_funcs;

	gfx_v6_0_set_ring_funcs(adev);

	gfx_v6_0_set_irq_funcs(adev);
@@ -3097,7 +3107,7 @@ static int gfx_v6_0_sw_init(void *handle) 
		return r;

	}



	r = gfx_v6_0_rlc_init(adev);

	r = adev->gfx.rlc.funcs->init(adev);

	if (r) {

		DRM_ERROR("Failed to init rlc BOs!\n");

		return r;
@@ -3148,7 +3158,7 @@ static int gfx_v6_0_sw_fini(void *handle) 
	for (i = 0; i < adev->gfx.num_compute_rings; i++)

		amdgpu_ring_fini(&adev->gfx.compute_ring[i]);



	gfx_v6_0_rlc_fini(adev);

	adev->gfx.rlc.funcs->fini(adev);



	return 0;

}
@@ -3160,7 +3170,7 @@ static int gfx_v6_0_hw_init(void *handle) 


	gfx_v6_0_constants_init(adev);



	r = gfx_v6_0_rlc_resume(adev);

	r = adev->gfx.rlc.funcs->resume(adev);

	if (r)

		return r;
@@ -3178,7 +3188,7 @@ static int gfx_v6_0_hw_fini(void *handle) 
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	gfx_v6_0_cp_enable(adev, false);

	gfx_v6_0_rlc_stop(adev);

	adev->gfx.rlc.funcs->stop(adev);

	gfx_v6_0_fini_pg(adev);



	return 0;

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

+18 −12
Original line number Diff line number Diff line
@@ -3298,7 +3298,7 @@ static int gfx_v7_0_rlc_init(struct amdgpu_device *adev) 
					      (void **)&adev->gfx.rlc.sr_ptr);

		if (r) {

			dev_warn(adev->dev, "(%d) create, pin or map of RLC sr bo failed\n", r);

			gfx_v7_0_rlc_fini(adev);

			adev->gfx.rlc.funcs->fini(adev);

			return r;

		}
@@ -3321,7 +3321,7 @@ static int gfx_v7_0_rlc_init(struct amdgpu_device *adev) 
					      (void **)&adev->gfx.rlc.cs_ptr);

		if (r) {

			dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);

			gfx_v7_0_rlc_fini(adev);

			adev->gfx.rlc.funcs->fini(adev);

			return r;

		}
@@ -3341,7 +3341,7 @@ static int gfx_v7_0_rlc_init(struct amdgpu_device *adev) 
					      (void **)&adev->gfx.rlc.cp_table_ptr);

		if (r) {

			dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r);

			gfx_v7_0_rlc_fini(adev);

			adev->gfx.rlc.funcs->fini(adev);

			return r;

		}
@@ -3529,13 +3529,13 @@ static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev) 
	adev->gfx.rlc_feature_version = le32_to_cpu(

					hdr->ucode_feature_version);



	gfx_v7_0_rlc_stop(adev);

	adev->gfx.rlc.funcs->stop(adev);



	/* disable CG */

	tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc;

	WREG32(mmRLC_CGCG_CGLS_CTRL, tmp);



	gfx_v7_0_rlc_reset(adev);

	adev->gfx.rlc.funcs->reset(adev);



	gfx_v7_0_init_pg(adev);
@@ -3566,7 +3566,7 @@ static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev) 
	if (adev->asic_type == CHIP_BONAIRE)

		WREG32(mmRLC_DRIVER_CPDMA_STATUS, 0);



	gfx_v7_0_rlc_start(adev);

	adev->gfx.rlc.funcs->start(adev);



	return 0;

}
@@ -4273,7 +4273,13 @@ static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs = { 


static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_funcs = {

	.enter_safe_mode = gfx_v7_0_enter_rlc_safe_mode,

	.exit_safe_mode = gfx_v7_0_exit_rlc_safe_mode

	.exit_safe_mode = gfx_v7_0_exit_rlc_safe_mode,

	.init = gfx_v7_0_rlc_init,

	.fini = gfx_v7_0_rlc_fini,

	.resume = gfx_v7_0_rlc_resume,

	.stop = gfx_v7_0_rlc_stop,

	.reset = gfx_v7_0_rlc_reset,

	.start = gfx_v7_0_rlc_start

};



static int gfx_v7_0_early_init(void *handle)
@@ -4524,7 +4530,7 @@ static int gfx_v7_0_sw_init(void *handle) 
		return r;

	}



	r = gfx_v7_0_rlc_init(adev);

	r = adev->gfx.rlc.funcs->init(adev);

	if (r) {

		DRM_ERROR("Failed to init rlc BOs!\n");

		return r;
@@ -4588,7 +4594,7 @@ static int gfx_v7_0_sw_fini(void *handle) 
		amdgpu_ring_fini(&adev->gfx.compute_ring[i]);



	gfx_v7_0_cp_compute_fini(adev);

	gfx_v7_0_rlc_fini(adev);

	adev->gfx.rlc.funcs->fini(adev);

	gfx_v7_0_mec_fini(adev);

	amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,

				&adev->gfx.rlc.clear_state_gpu_addr,
@@ -4611,7 +4617,7 @@ static int gfx_v7_0_hw_init(void *handle) 
	gfx_v7_0_constants_init(adev);



	/* init rlc */

	r = gfx_v7_0_rlc_resume(adev);

	r = adev->gfx.rlc.funcs->resume(adev);

	if (r)

		return r;
@@ -4629,7 +4635,7 @@ static int gfx_v7_0_hw_fini(void *handle) 
	amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);

	amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);

	gfx_v7_0_cp_enable(adev, false);

	gfx_v7_0_rlc_stop(adev);

	adev->gfx.rlc.funcs->stop(adev);

	gfx_v7_0_fini_pg(adev);



	return 0;
@@ -4714,7 +4720,7 @@ static int gfx_v7_0_soft_reset(void *handle) 
		gfx_v7_0_update_cg(adev, false);



		/* stop the rlc */

		gfx_v7_0_rlc_stop(adev);

		adev->gfx.rlc.funcs->stop(adev);



		/* Disable GFX parsing/prefetching */

		WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

+17 −11
Original line number Diff line number Diff line
@@ -1376,7 +1376,7 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev) 
					      (void **)&adev->gfx.rlc.cs_ptr);

		if (r) {

			dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);

			gfx_v8_0_rlc_fini(adev);

			adev->gfx.rlc.funcs->fini(adev);

			return r;

		}
@@ -2073,7 +2073,7 @@ static int gfx_v8_0_sw_init(void *handle) 
		return r;

	}



	r = gfx_v8_0_rlc_init(adev);

	r = adev->gfx.rlc.funcs->init(adev);

	if (r) {

		DRM_ERROR("Failed to init rlc BOs!\n");

		return r;
@@ -2166,7 +2166,7 @@ static int gfx_v8_0_sw_fini(void *handle) 
	amdgpu_gfx_kiq_fini(adev);



	gfx_v8_0_mec_fini(adev);

	gfx_v8_0_rlc_fini(adev);

	adev->gfx.rlc.funcs->fini(adev);

	amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,

				&adev->gfx.rlc.clear_state_gpu_addr,

				(void **)&adev->gfx.rlc.cs_ptr);
@@ -4160,10 +4160,10 @@ static void gfx_v8_0_rlc_start(struct amdgpu_device *adev) 


static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)

{

	gfx_v8_0_rlc_stop(adev);

	gfx_v8_0_rlc_reset(adev);

	adev->gfx.rlc.funcs->stop(adev);

	adev->gfx.rlc.funcs->reset(adev);

	gfx_v8_0_init_pg(adev);

	gfx_v8_0_rlc_start(adev);

	adev->gfx.rlc.funcs->start(adev);



	return 0;

}
@@ -4845,7 +4845,7 @@ static int gfx_v8_0_hw_init(void *handle) 
	gfx_v8_0_init_golden_registers(adev);

	gfx_v8_0_constants_init(adev);



	r = gfx_v8_0_rlc_resume(adev);

	r = adev->gfx.rlc.funcs->resume(adev);

	if (r)

		return r;
@@ -4957,7 +4957,7 @@ static int gfx_v8_0_hw_fini(void *handle) 
	else

		pr_err("cp is busy, skip halt cp\n");

	if (!gfx_v8_0_wait_for_rlc_idle(adev))

		gfx_v8_0_rlc_stop(adev);

		adev->gfx.rlc.funcs->stop(adev);

	else

		pr_err("rlc is busy, skip halt rlc\n");

	adev->gfx.rlc.funcs->exit_safe_mode(adev);
@@ -5049,7 +5049,7 @@ static int gfx_v8_0_pre_soft_reset(void *handle) 
	srbm_soft_reset = adev->gfx.srbm_soft_reset;



	/* stop the rlc */

	gfx_v8_0_rlc_stop(adev);

	adev->gfx.rlc.funcs->stop(adev);



	if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||

	    REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX))
@@ -5175,7 +5175,7 @@ static int gfx_v8_0_post_soft_reset(void *handle) 
	    REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX))

		gfx_v8_0_cp_gfx_resume(adev);



	gfx_v8_0_rlc_start(adev);

	adev->gfx.rlc.funcs->start(adev);



	return 0;

}
@@ -5632,7 +5632,13 @@ static void iceland_exit_rlc_safe_mode(struct amdgpu_device *adev) 


static const struct amdgpu_rlc_funcs iceland_rlc_funcs = {

	.enter_safe_mode = iceland_enter_rlc_safe_mode,

	.exit_safe_mode = iceland_exit_rlc_safe_mode

	.exit_safe_mode = iceland_exit_rlc_safe_mode,

	.init = gfx_v8_0_rlc_init,

	.fini = gfx_v8_0_rlc_fini,

	.resume = gfx_v8_0_rlc_resume,

	.stop = gfx_v8_0_rlc_stop,

	.reset = gfx_v8_0_rlc_reset,

	.start = gfx_v8_0_rlc_start

};



static void gfx_v8_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+18 −12
Original line number Diff line number Diff line
@@ -1147,7 +1147,7 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev) 
		if (r) {

			dev_err(adev->dev, "(%d) failed to create rlc csb bo\n",

				r);

			gfx_v9_0_rlc_fini(adev);

			adev->gfx.rlc.funcs->fini(adev);

			return r;

		}

		/* set up the cs buffer */
@@ -1169,7 +1169,7 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev) 
		if (r) {

			dev_err(adev->dev,

				"(%d) failed to create cp table bo\n", r);

			gfx_v9_0_rlc_fini(adev);

			adev->gfx.rlc.funcs->fini(adev);

			return r;

		}
@@ -1733,7 +1733,7 @@ static int gfx_v9_0_sw_init(void *handle) 
		return r;

	}



	r = gfx_v9_0_rlc_init(adev);

	r = adev->gfx.rlc.funcs->init(adev);

	if (r) {

		DRM_ERROR("Failed to init rlc BOs!\n");

		return r;
@@ -2483,12 +2483,12 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev) 
		return 0;

	}



	gfx_v9_0_rlc_stop(adev);

	adev->gfx.rlc.funcs->stop(adev);



	/* disable CG */

	WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);



	gfx_v9_0_rlc_reset(adev);

	adev->gfx.rlc.funcs->reset(adev);



	gfx_v9_0_init_pg(adev);
@@ -2521,7 +2521,7 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev) 
			gfx_v9_0_enable_lbpw(adev, false);

	}



	gfx_v9_0_rlc_start(adev);

	adev->gfx.rlc.funcs->start(adev);



	return 0;

}
@@ -3344,7 +3344,7 @@ static int gfx_v9_0_hw_init(void *handle) 
	if (r)

		return r;



	r = gfx_v9_0_rlc_resume(adev);

	r = adev->gfx.rlc.funcs->resume(adev);

	if (r)

		return r;
@@ -3424,7 +3424,7 @@ static int gfx_v9_0_hw_fini(void *handle) 
	}



	gfx_v9_0_cp_enable(adev, false);

	gfx_v9_0_rlc_stop(adev);

	adev->gfx.rlc.funcs->stop(adev);



	gfx_v9_0_csb_vram_unpin(adev);
@@ -3499,7 +3499,7 @@ static int gfx_v9_0_soft_reset(void *handle) 


	if (grbm_soft_reset) {

		/* stop the rlc */

		gfx_v9_0_rlc_stop(adev);

		adev->gfx.rlc.funcs->stop(adev);



		/* Disable GFX parsing/prefetching */

		gfx_v9_0_cp_gfx_enable(adev, false);
@@ -3655,7 +3655,7 @@ static void gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device *adev) 
static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,

						bool enable)

{

	gfx_v9_0_enter_rlc_safe_mode(adev);

	adev->gfx.rlc.funcs->enter_safe_mode(adev);



	if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {

		gfx_v9_0_enable_gfx_cg_power_gating(adev, true);
@@ -3666,7 +3666,7 @@ static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev, 
		gfx_v9_0_enable_gfx_pipeline_powergating(adev, false);

	}



	gfx_v9_0_exit_rlc_safe_mode(adev);

	adev->gfx.rlc.funcs->exit_safe_mode(adev);

}



static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev,
@@ -3882,7 +3882,13 @@ static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev, 


static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {

	.enter_safe_mode = gfx_v9_0_enter_rlc_safe_mode,

	.exit_safe_mode = gfx_v9_0_exit_rlc_safe_mode

	.exit_safe_mode = gfx_v9_0_exit_rlc_safe_mode,

	.init = gfx_v9_0_rlc_init,

	.fini = gfx_v9_0_rlc_fini,

	.resume = gfx_v9_0_rlc_resume,

	.stop = gfx_v9_0_rlc_stop,

	.reset = gfx_v9_0_rlc_reset,

	.start = gfx_v9_0_rlc_start

};



static int gfx_v9_0_set_powergating_state(void *handle,