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Commit f716cd75 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "msm: ep-pcie: Correct two CAP reg offsets"

parents ff3d25b2 c150d993

drivers/platform/msm/ep_pcie/ep_pcie_com.h

+2 −2
Original line number Diff line number Diff line
@@ -105,8 +105,8 @@ 
#define PCIE20_CAP_LINKCTRLSTATUS      0x80

#define PCIE20_DEVICE_CONTROL2_STATUS2 0x98

#define PCIE20_LINK_CONTROL2_LINK_STATUS2 0xA0

#define PCIE20_L1SUB_CAPABILITY        0x154

#define PCIE20_L1SUB_CONTROL1          0x158

#define PCIE20_L1SUB_CAPABILITY        0x234

#define PCIE20_L1SUB_CONTROL1          0x238

#define PCIE20_BUS_DISCONNECT_STATUS   0x68c

#define PCIE20_ACK_F_ASPM_CTRL_REG     0x70C

#define PCIE20_MASK_ACK_N_FTS          0xff00

drivers/platform/msm/ep_pcie/ep_pcie_core.c

+9 −4
Original line number Diff line number Diff line
@@ -657,10 +657,6 @@ static void ep_pcie_core_init(struct ep_pcie_dev_t *dev, bool configured) 
				PCIE20_LINK_CONTROL2_LINK_STATUS2,

				0xf, dev->link_speed);



		EP_PCIE_DBG2(dev, "PCIe V%d: Allow L1 after D3_COLD->D0\n",

				dev->rev);

		ep_pcie_write_mask(dev->parf + PCIE20_PARF_PM_CTRL, BIT(5), 0);



		EP_PCIE_DBG2(dev, "PCIe V%d: Clear disconn_req after D3_COLD\n",

			     dev->rev);

		ep_pcie_write_reg_field(dev->tcsr_perst_en,
@@ -1976,6 +1972,11 @@ int ep_pcie_core_enable_endpoint(enum ep_pcie_options opt) 
			dev->rev, retries,

			BME_TIMEOUT_US_MIN * retries / 1000);

		ep_pcie_enumeration_complete(dev);



		EP_PCIE_DBG2(dev, "PCIe V%d: Allow L1 after BME is set\n",

				dev->rev);

		ep_pcie_write_mask(dev->parf + PCIE20_PARF_PM_CTRL, BIT(5), 0);



		/* expose BAR to user space to identify modem */

		ep_pcie_bar0_address =

			readl_relaxed(dev->dm_core + PCIE20_BAR0);
@@ -2149,6 +2150,10 @@ static irqreturn_t ep_pcie_handle_bme_irq(int irq, void *data) 
				dev->rev);

			ep_pcie_notify_event(dev, EP_PCIE_EVENT_LINKUP);

		}



		EP_PCIE_DBG2(dev, "PCIe V%d: Allow L1 after BME is set\n",

				dev->rev);

		ep_pcie_write_mask(dev->parf + PCIE20_PARF_PM_CTRL, BIT(5), 0);

	} else {

		EP_PCIE_DBG(dev,

				"PCIe V%d:BME is still disabled\n", dev->rev);