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Commit f65a9c5b authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
Browse files

drm/i915: Parametrize PALETTE and LGC_PALETTE 



Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent c039b7f2

drivers/gpu/drm/i915/i915_reg.h

+3 −3
Original line number Diff line number Diff line
@@ -2485,8 +2485,8 @@ enum skl_disp_power_wells { 
#define PALETTE_A_OFFSET 0xa000

#define PALETTE_B_OFFSET 0xa800

#define CHV_PALETTE_C_OFFSET 0xc000

#define PALETTE(pipe) (dev_priv->info.palette_offsets[pipe] + \

		       dev_priv->info.display_mmio_offset)

#define PALETTE(pipe, i) (dev_priv->info.palette_offsets[pipe] + \

			  dev_priv->info.display_mmio_offset + (i) * 4)



/* MCH MMIO space */
@@ -5641,7 +5641,7 @@ enum skl_disp_power_wells { 
/* legacy palette */

#define _LGC_PALETTE_A           0x4a000

#define _LGC_PALETTE_B           0x4a800

#define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)

#define LGC_PALETTE(pipe, i) (_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)



#define _GAMMA_MODE_A		0x4a480

#define _GAMMA_MODE_B		0x4ac80

drivers/gpu/drm/i915/intel_display.c

+8 −6
Original line number Diff line number Diff line
@@ -4593,7 +4593,6 @@ static void intel_crtc_load_lut(struct drm_crtc *crtc) 
	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	enum pipe pipe = intel_crtc->pipe;

	int palreg = PALETTE(pipe);

	int i;

	bool reenable_ips = false;
@@ -4608,10 +4607,6 @@ static void intel_crtc_load_lut(struct drm_crtc *crtc) 
			assert_pll_enabled(dev_priv, pipe);

	}



	/* use legacy palette for Ironlake */

	if (!HAS_GMCH_DISPLAY(dev))

		palreg = LGC_PALETTE(pipe);



	/* Workaround : Do not read or write the pipe palette/gamma data while

	 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.

	 */
@@ -4623,7 +4618,14 @@ static void intel_crtc_load_lut(struct drm_crtc *crtc) 
	}



	for (i = 0; i < 256; i++) {

		I915_WRITE(palreg + 4 * i,

		u32 palreg;



		if (HAS_GMCH_DISPLAY(dev))

			palreg = PALETTE(pipe, i);

		else

			palreg = LGC_PALETTE(pipe, i);



		I915_WRITE(palreg,

			   (intel_crtc->lut_r[i] << 16) |

			   (intel_crtc->lut_g[i] << 8) |

			   intel_crtc->lut_b[i]);