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Commit f584e323 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add UFS ICE HW Node for SA8195 and SM8150"

parents b82e91b4 b80d5e69

bindings/crypto/msm/ice.txt

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* Inline Crypto Engine (ICE)



Required properties:

  - compatible : should be "qcom,ice"

  - reg : <register mapping>



Optional properties:

  - interrupt-names     	: name describing the interrupts for ICE IRQ

  - interrupts          	: <interrupt mapping for ICE IRQ>

  - qcom,enable-ice-clk 	: should enable clocks for ICE HW

  - clocks              	: List of phandle and clock specifier pairs

  - clock-names         	: List of clock input name strings sorted in the same

                          	  order as the clocks property.

  - qocm,op-freq-hz     	: max clock speed sorted in the same order as the clocks

                          	  property.

  - qcom,instance-type  	: describe the storage type for which ICE node is defined

			 	  currently, only "ufs" and "sdcc" are supported storage type

  - vdd-hba-supply		: regulated supply to be used by ICE HW

  - qcom,bus-vector-names	: bus vectors mapping



Example:

        ufs_ice: ufsice@630000 {

                compatible = "qcom,ice";

                reg = <0x630000 0x8000>;

                interrupt-names = "ufs_ice_nonsec_level_irq", "ufs_ice_sec_level_irq";

                interrupts = <0 258 0>, <0 257 0>;

                qcom,enable-ice-clk;

                clock-names = "ice_core_clk_src", "ice_core_clk";

                clocks = <&clock_gcc clk_ufs_ice_core_clk_src>,

                         <&clock_gcc clk_gcc_ufs_ice_core_clk>;

                qcom,op-freq-hz = <300000000>, <0>;

		qcom,instance-type = "ufs";

                status = "disabled";

        };



	ufs_card_ice: ufscardice@1db0000 {

		compatible = "qcom,ice_card";

		reg = <0x1db0000 0x8000>;

		qcom,enable-ice-clk;

		clock-names = "ufs_core_clk", "bus_clk",

			      "iface_clk", "ice_core_clk";

		clocks = <&clock_gcc GCC_UFS_CARD_AXI_CLK>,

			 <&clock_gcc GCC_UFS_CARD_CLKREF_CLK>,

			 <&clock_gcc GCC_UFS_CARD_AHB_CLK>,

			 <&clock_gcc GCC_UFS_CARD_ICE_CORE_CLK>;

		qcom,op-freq-hz = <0>, <0>, <0>, <300000000>;

		vdd-hba-supply = <&ufs_card_gdsc>;

		qcom,bus-vector-names = "MIN",

					"MAX";

		qcom,instance-type = "ufs_card";

	};

qcom/sdmshrike.dtsi

+16 −0
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@@ -1098,6 +1098,22 @@ 
		clock-frequency = <32768>;

	};



	ufs_ice: ufsice@1d90000 {

		compatible = "qcom,ice";

		reg = <0x1d90000 0x8000>;

		qcom,enable-ice-clk;

		clock-names = "ufs_core_clk",

			      "iface_clk", "ice_core_clk";

		clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,

			 <&gcc GCC_UFS_PHY_AHB_CLK>,

			 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;

		qcom,op-freq-hz = <0>, <0>, <300000000>;

		vdd-hba-supply = <&ufs_phy_gdsc>;

		qcom,bus-vector-names = "MIN",

					"MAX";

		qcom,instance-type = "ufs";

	};



	disp_rsc: rsc@af20000 {

		label = "disp_rsc";

		compatible = "qcom,rpmh-rsc";

qcom/sm8150.dtsi

+20 −0
Original line number Diff line number Diff line
@@ -1501,6 +1501,26 @@ 
		reg = <0x17c0000c 0x4>;

	};







	ufs_ice: ufsice@1d90000 {

		compatible = "qcom,ice";

		reg = <0x1d90000 0x8000>;

		qcom,enable-ice-clk;

		clock-names = "ufs_core_clk", "bus_clk",

			      "iface_clk", "ice_core_clk";

		clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,

			 <&gcc GCC_UFS_MEM_CLKREF_CLK>,

			 <&gcc GCC_UFS_PHY_AHB_CLK>,

			 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;

		qcom,op-freq-hz = <0>, <0>, <0>, <300000000>;

		vdd-hba-supply = <&ufs_phy_gdsc>;

		qcom,bus-vector-names = "MIN",

					"MAX";

		qcom,instance-type = "ufs";

	};





	apss_shared: mailbox@17c00000 {

		compatible = "qcom,sm8150-apss-shared";

		reg = <0x17c00000 0x1000>;