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Commit b80d5e69 authored by Victor Zaharchuk's avatar Victor Zaharchuk Committed by Victor
Browse files

ARM: dts: msm: Add UFS ICE HW Node for SA8195 and SM8150 

Add required dtsi changes for UFS-ICE HW enablement for SA8195 and SM8150.

Change-Id: I0cf94e9d87cf3785ecf2d99c273694f8c44e2645
parent dd0f1949

qcom/sdmshrike.dtsi

+16 −0
Original line number Diff line number Diff line
@@ -1098,6 +1098,22 @@ 
		clock-frequency = <32768>;

	};



	ufs_ice: ufsice@1d90000 {

		compatible = "qcom,ice";

		reg = <0x1d90000 0x8000>;

		qcom,enable-ice-clk;

		clock-names = "ufs_core_clk",

			      "iface_clk", "ice_core_clk";

		clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,

			 <&gcc GCC_UFS_PHY_AHB_CLK>,

			 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;

		qcom,op-freq-hz = <0>, <0>, <300000000>;

		vdd-hba-supply = <&ufs_phy_gdsc>;

		qcom,bus-vector-names = "MIN",

					"MAX";

		qcom,instance-type = "ufs";

	};



	disp_rsc: rsc@af20000 {

		label = "disp_rsc";

		compatible = "qcom,rpmh-rsc";

qcom/sm8150.dtsi

+20 −0
Original line number Diff line number Diff line
@@ -1501,6 +1501,26 @@ 
		reg = <0x17c0000c 0x4>;

	};







	ufs_ice: ufsice@1d90000 {

		compatible = "qcom,ice";

		reg = <0x1d90000 0x8000>;

		qcom,enable-ice-clk;

		clock-names = "ufs_core_clk", "bus_clk",

			      "iface_clk", "ice_core_clk";

		clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,

			 <&gcc GCC_UFS_MEM_CLKREF_CLK>,

			 <&gcc GCC_UFS_PHY_AHB_CLK>,

			 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;

		qcom,op-freq-hz = <0>, <0>, <0>, <300000000>;

		vdd-hba-supply = <&ufs_phy_gdsc>;

		qcom,bus-vector-names = "MIN",

					"MAX";

		qcom,instance-type = "ufs";

	};





	apss_shared: mailbox@17c00000 {

		compatible = "qcom,sm8150-apss-shared";

		reg = <0x17c00000 0x1000>;