Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit f3ce44a0 authored by Lucas De Marchi's avatar Lucas De Marchi Committed by Rodrigo Vivi
Browse files

drm/i915: merge gen checks to use range 



Instead of using IS_GEN() for consecutive gen checks, let's pass the
range to IS_GEN_RANGE(). By code inspection these were the ranges deemed
necessary for spatch:

@@
expression e;
@@
(
- IS_GEN(e, 3) || IS_GEN(e, 2)
+ IS_GEN_RANGE(e, 2, 3)
|
- IS_GEN(e, 3) || IS_GEN(e, 4)
+ IS_GEN_RANGE(e, 3, 4)
|
- IS_GEN(e, 5) || IS_GEN(e, 6)
+ IS_GEN_RANGE(e, 5, 6)
|
- IS_GEN(e, 6) || IS_GEN(e, 7)
+ IS_GEN_RANGE(e, 6, 7)
|
- IS_GEN(e, 7) || IS_GEN(e, 8)
+ IS_GEN_RANGE(e, 7, 8)
|
- IS_GEN(e, 8) || IS_GEN(e, 9)
+ IS_GEN_RANGE(e, 8, 9)
|
- IS_GEN(e, 10) || IS_GEN(e, 9)
+ IS_GEN_RANGE(e, 9, 10)
|
- IS_GEN(e, 9) || IS_GEN(e, 10)
+ IS_GEN_RANGE(e, 9, 10)
)

After conversion, checking we don't have any missing IS_GEN_RANGE() ||
IS_GEN() was also done.

Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181212181044.15886-3-lucas.demarchi@intel.com
parent cf819eff

drivers/gpu/drm/i915/i915_debugfs.c

+3 −3
Original line number Diff line number Diff line
@@ -2040,7 +2040,7 @@ static int i915_swizzle_info(struct seq_file *m, void *data) 
	seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",

		   swizzle_string(dev_priv->mm.bit_6_swizzle_y));



	if (IS_GEN(dev_priv, 3) || IS_GEN(dev_priv, 4)) {

	if (IS_GEN_RANGE(dev_priv, 3, 4)) {

		seq_printf(m, "DDC = 0x%08x\n",

			   I915_READ(DCC));

		seq_printf(m, "DDC2 = 0x%08x\n",
@@ -4274,7 +4274,7 @@ i915_cache_sharing_get(void *data, u64 *val) 
	struct drm_i915_private *dev_priv = data;

	u32 snpcr;



	if (!(IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)))

	if (!(IS_GEN_RANGE(dev_priv, 6, 7)))

		return -ENODEV;



	intel_runtime_pm_get(dev_priv);
@@ -4294,7 +4294,7 @@ i915_cache_sharing_set(void *data, u64 val) 
	struct drm_i915_private *dev_priv = data;

	u32 snpcr;



	if (!(IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)))

	if (!(IS_GEN_RANGE(dev_priv, 6, 7)))

		return -ENODEV;



	if (val > 3)

drivers/gpu/drm/i915/i915_gpu_error.c

+1 −1
Original line number Diff line number Diff line
@@ -1753,7 +1753,7 @@ static void capture_reg_state(struct i915_gpu_state *error) 
		error->ccid = I915_READ(CCID);



	/* 3: Feature specific registers */

	if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)) {

	if (IS_GEN_RANGE(dev_priv, 6, 7)) {

		error->gam_ecochk = I915_READ(GAM_ECOCHK);

		error->gac_eco = I915_READ(GAC_ECO_BITS);

	}

drivers/gpu/drm/i915/i915_perf.c

+1 −1
Original line number Diff line number Diff line
@@ -3415,7 +3415,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv) 
		dev_priv->perf.oa.ops.read = gen8_oa_read;

		dev_priv->perf.oa.ops.oa_hw_tail_read = gen8_oa_hw_tail_read;



		if (IS_GEN(dev_priv, 8) || IS_GEN(dev_priv, 9)) {

		if (IS_GEN_RANGE(dev_priv, 8, 9)) {

			dev_priv->perf.oa.ops.is_valid_b_counter_reg =

				gen7_is_valid_b_counter_addr;

			dev_priv->perf.oa.ops.is_valid_mux_reg =

drivers/gpu/drm/i915/intel_crt.c

+1 −1
Original line number Diff line number Diff line
@@ -322,7 +322,7 @@ intel_crt_mode_valid(struct drm_connector *connector, 
		 * DAC limit supposedly 355 MHz.

		 */

		max_clock = 270000;

	else if (IS_GEN(dev_priv, 3) || IS_GEN(dev_priv, 4))

	else if (IS_GEN_RANGE(dev_priv, 3, 4))

		max_clock = 400000;

	else

		max_clock = 350000;

drivers/gpu/drm/i915/intel_device_info.c

+1 −1
Original line number Diff line number Diff line
@@ -787,7 +787,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info) 
		DRM_INFO("Display disabled (module parameter)\n");

		info->num_pipes = 0;

	} else if (HAS_DISPLAY(dev_priv) &&

		   (IS_GEN(dev_priv, 7) || IS_GEN(dev_priv, 8)) &&

		   (IS_GEN_RANGE(dev_priv, 7, 8)) &&

		   HAS_PCH_SPLIT(dev_priv)) {

		u32 fuse_strap = I915_READ(FUSE_STRAP);

		u32 sfuse_strap = I915_READ(SFUSE_STRAP);