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Commit cf819eff authored by Lucas De Marchi's avatar Lucas De Marchi Committed by Rodrigo Vivi
Browse files

drm/i915: replace IS_GEN<N> with IS_GEN(..., N) 



Define IS_GEN() similarly to our IS_GEN_RANGE(). but use gen instead of
gen_mask to do the comparison. Now callers can pass then gen as a parameter,
so we don't require one macro for each gen.

The following spatch was used to convert the users of these macros:

@@
expression e;
@@
(
- IS_GEN2(e)
+ IS_GEN(e, 2)
|
- IS_GEN3(e)
+ IS_GEN(e, 3)
|
- IS_GEN4(e)
+ IS_GEN(e, 4)
|
- IS_GEN5(e)
+ IS_GEN(e, 5)
|
- IS_GEN6(e)
+ IS_GEN(e, 6)
|
- IS_GEN7(e)
+ IS_GEN(e, 7)
|
- IS_GEN8(e)
+ IS_GEN(e, 8)
|
- IS_GEN9(e)
+ IS_GEN(e, 9)
|
- IS_GEN10(e)
+ IS_GEN(e, 10)
|
- IS_GEN11(e)
+ IS_GEN(e, 11)
)

v2: use IS_GEN rather than GT_GEN and compare to info.gen rather than
    using the bitmask

Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181212181044.15886-2-lucas.demarchi@intel.com
parent 00690008

drivers/gpu/drm/i915/gvt/vgpu.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -148,10 +148,10 @@ int intel_gvt_init_vgpu_types(struct intel_gvt *gvt) 
		gvt->types[i].avail_instance = min(low_avail / vgpu_types[i].low_mm,

		gvt->types[i].avail_instance = min(low_avail / vgpu_types[i].low_mm,

						   high_avail / vgpu_types[i].high_mm);

						   high_avail / vgpu_types[i].high_mm);





		if (IS_GEN8(gvt->dev_priv))

		if (IS_GEN(gvt->dev_priv, 8))

			sprintf(gvt->types[i].name, "GVTg_V4_%s",

			sprintf(gvt->types[i].name, "GVTg_V4_%s",

						vgpu_types[i].name);

						vgpu_types[i].name);

		else if (IS_GEN9(gvt->dev_priv))

		else if (IS_GEN(gvt->dev_priv, 9))

			sprintf(gvt->types[i].name, "GVTg_V5_%s",

			sprintf(gvt->types[i].name, "GVTg_V5_%s",

						vgpu_types[i].name);

						vgpu_types[i].name);

drivers/gpu/drm/i915/i915_cmd_parser.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -865,7 +865,7 @@ void intel_engine_init_cmd_parser(struct intel_engine_cs *engine) 
	int cmd_table_count;

	int cmd_table_count;

	int ret;

	int ret;





	if (!IS_GEN7(engine->i915))

	if (!IS_GEN(engine->i915, 7))

		return;

		return;





	switch (engine->id) {

	switch (engine->id) {

drivers/gpu/drm/i915/i915_debugfs.c

+8 −8
Original line number Original line Diff line number Diff line
@@ -1070,7 +1070,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused) 




	intel_runtime_pm_get(dev_priv);

	intel_runtime_pm_get(dev_priv);





	if (IS_GEN5(dev_priv)) {

	if (IS_GEN(dev_priv, 5)) {

		u16 rgvswctl = I915_READ16(MEMSWCTL);

		u16 rgvswctl = I915_READ16(MEMSWCTL);

		u16 rgvstat = I915_READ16(MEMSTAT_ILK);

		u16 rgvstat = I915_READ16(MEMSTAT_ILK);
@@ -1791,7 +1791,7 @@ static int i915_emon_status(struct seq_file *m, void *unused) 
	unsigned long temp, chipset, gfx;

	unsigned long temp, chipset, gfx;

	int ret;

	int ret;





	if (!IS_GEN5(dev_priv))

	if (!IS_GEN(dev_priv, 5))

		return -ENODEV;

		return -ENODEV;





	intel_runtime_pm_get(dev_priv);

	intel_runtime_pm_get(dev_priv);
@@ -2040,7 +2040,7 @@ static int i915_swizzle_info(struct seq_file *m, void *data) 
	seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",

	seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",

		   swizzle_string(dev_priv->mm.bit_6_swizzle_y));

		   swizzle_string(dev_priv->mm.bit_6_swizzle_y));





	if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) {

	if (IS_GEN(dev_priv, 3) || IS_GEN(dev_priv, 4)) {

		seq_printf(m, "DDC = 0x%08x\n",

		seq_printf(m, "DDC = 0x%08x\n",

			   I915_READ(DCC));

			   I915_READ(DCC));

		seq_printf(m, "DDC2 = 0x%08x\n",

		seq_printf(m, "DDC2 = 0x%08x\n",
@@ -2125,12 +2125,12 @@ static void gen6_ppgtt_info(struct seq_file *m, 
	struct intel_engine_cs *engine;

	struct intel_engine_cs *engine;

	enum intel_engine_id id;

	enum intel_engine_id id;





	if (IS_GEN6(dev_priv))

	if (IS_GEN(dev_priv, 6))

		seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));

		seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));





	for_each_engine(engine, dev_priv, id) {

	for_each_engine(engine, dev_priv, id) {

		seq_printf(m, "%s\n", engine->name);

		seq_printf(m, "%s\n", engine->name);

		if (IS_GEN7(dev_priv))

		if (IS_GEN(dev_priv, 7))

			seq_printf(m, "GFX_MODE: 0x%08x\n",

			seq_printf(m, "GFX_MODE: 0x%08x\n",

				   I915_READ(RING_MODE_GEN7(engine)));

				   I915_READ(RING_MODE_GEN7(engine)));

		seq_printf(m, "PP_DIR_BASE: 0x%08x\n",

		seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
@@ -4274,7 +4274,7 @@ i915_cache_sharing_get(void *data, u64 *val) 
	struct drm_i915_private *dev_priv = data;

	struct drm_i915_private *dev_priv = data;

	u32 snpcr;

	u32 snpcr;





	if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))

	if (!(IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)))

		return -ENODEV;

		return -ENODEV;





	intel_runtime_pm_get(dev_priv);

	intel_runtime_pm_get(dev_priv);
@@ -4294,7 +4294,7 @@ i915_cache_sharing_set(void *data, u64 val) 
	struct drm_i915_private *dev_priv = data;

	struct drm_i915_private *dev_priv = data;

	u32 snpcr;

	u32 snpcr;





	if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))

	if (!(IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)))

		return -ENODEV;

		return -ENODEV;





	if (val > 3)

	if (val > 3)
@@ -4551,7 +4551,7 @@ static int i915_sseu_status(struct seq_file *m, void *unused) 
		cherryview_sseu_device_status(dev_priv, &sseu);

		cherryview_sseu_device_status(dev_priv, &sseu);

	} else if (IS_BROADWELL(dev_priv)) {

	} else if (IS_BROADWELL(dev_priv)) {

		broadwell_sseu_device_status(dev_priv, &sseu);

		broadwell_sseu_device_status(dev_priv, &sseu);

	} else if (IS_GEN9(dev_priv)) {

	} else if (IS_GEN(dev_priv, 9)) {

		gen9_sseu_device_status(dev_priv, &sseu);

		gen9_sseu_device_status(dev_priv, &sseu);

	} else if (INTEL_GEN(dev_priv) >= 10) {

	} else if (INTEL_GEN(dev_priv) >= 10) {

		gen10_sseu_device_status(dev_priv, &sseu);

		gen10_sseu_device_status(dev_priv, &sseu);

drivers/gpu/drm/i915/i915_drv.c

+9 −9
Original line number Original line Diff line number Diff line
@@ -132,15 +132,15 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id) 
	switch (id) {

	switch (id) {

	case INTEL_PCH_IBX_DEVICE_ID_TYPE:

	case INTEL_PCH_IBX_DEVICE_ID_TYPE:

		DRM_DEBUG_KMS("Found Ibex Peak PCH\n");

		DRM_DEBUG_KMS("Found Ibex Peak PCH\n");

		WARN_ON(!IS_GEN5(dev_priv));

		WARN_ON(!IS_GEN(dev_priv, 5));

		return PCH_IBX;

		return PCH_IBX;

	case INTEL_PCH_CPT_DEVICE_ID_TYPE:

	case INTEL_PCH_CPT_DEVICE_ID_TYPE:

		DRM_DEBUG_KMS("Found CougarPoint PCH\n");

		DRM_DEBUG_KMS("Found CougarPoint PCH\n");

		WARN_ON(!IS_GEN6(dev_priv) && !IS_IVYBRIDGE(dev_priv));

		WARN_ON(!IS_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv));

		return PCH_CPT;

		return PCH_CPT;

	case INTEL_PCH_PPT_DEVICE_ID_TYPE:

	case INTEL_PCH_PPT_DEVICE_ID_TYPE:

		DRM_DEBUG_KMS("Found PantherPoint PCH\n");

		DRM_DEBUG_KMS("Found PantherPoint PCH\n");

		WARN_ON(!IS_GEN6(dev_priv) && !IS_IVYBRIDGE(dev_priv));

		WARN_ON(!IS_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv));

		/* PantherPoint is CPT compatible */

		/* PantherPoint is CPT compatible */

		return PCH_CPT;

		return PCH_CPT;

	case INTEL_PCH_LPT_DEVICE_ID_TYPE:

	case INTEL_PCH_LPT_DEVICE_ID_TYPE:
@@ -217,9 +217,9 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv) 
	 * make an educated guess as to which PCH is really there.

	 * make an educated guess as to which PCH is really there.

	 */

	 */





	if (IS_GEN5(dev_priv))

	if (IS_GEN(dev_priv, 5))

		id = INTEL_PCH_IBX_DEVICE_ID_TYPE;

		id = INTEL_PCH_IBX_DEVICE_ID_TYPE;

	else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))

	else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))

		id = INTEL_PCH_CPT_DEVICE_ID_TYPE;

		id = INTEL_PCH_CPT_DEVICE_ID_TYPE;

	else if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))

	else if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))

		id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;

		id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
@@ -966,7 +966,7 @@ static int i915_mmio_setup(struct drm_i915_private *dev_priv) 
	int mmio_bar;

	int mmio_bar;

	int mmio_size;

	int mmio_size;





	mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;

	mmio_bar = IS_GEN(dev_priv, 2) ? 1 : 0;

	/*

	/*

	 * Before gen4, the registers and the GTT are behind different BARs.

	 * Before gen4, the registers and the GTT are behind different BARs.

	 * However, from gen4 onwards, the registers and the GTT are shared

	 * However, from gen4 onwards, the registers and the GTT are shared
@@ -1341,7 +1341,7 @@ intel_get_dram_info(struct drm_i915_private *dev_priv) 
	/* Need to calculate bandwidth only for Gen9 */

	/* Need to calculate bandwidth only for Gen9 */

	if (IS_BROXTON(dev_priv))

	if (IS_BROXTON(dev_priv))

		ret = bxt_get_dram_info(dev_priv);

		ret = bxt_get_dram_info(dev_priv);

	else if (IS_GEN9(dev_priv))

	else if (IS_GEN(dev_priv, 9))

		ret = skl_get_dram_info(dev_priv);

		ret = skl_get_dram_info(dev_priv);

	else

	else

		ret = skl_dram_get_channels_info(dev_priv);

		ret = skl_dram_get_channels_info(dev_priv);
@@ -1436,7 +1436,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv) 
	pci_set_master(pdev);

	pci_set_master(pdev);





	/* overlay on gen2 is broken and can't address above 1G */

	/* overlay on gen2 is broken and can't address above 1G */

	if (IS_GEN2(dev_priv)) {

	if (IS_GEN(dev_priv, 2)) {

		ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));

		ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));

		if (ret) {

		if (ret) {

			DRM_ERROR("failed to set DMA mask\n");

			DRM_ERROR("failed to set DMA mask\n");
@@ -1574,7 +1574,7 @@ static void i915_driver_register(struct drm_i915_private *dev_priv) 
		acpi_video_register();

		acpi_video_register();

	}

	}





	if (IS_GEN5(dev_priv))

	if (IS_GEN(dev_priv, 5))

		intel_gpu_ips_init(dev_priv);

		intel_gpu_ips_init(dev_priv);





	intel_audio_init(dev_priv);

	intel_audio_init(dev_priv);

drivers/gpu/drm/i915/i915_drv.h

+8 −21
Original line number Original line Diff line number Diff line
@@ -2214,6 +2214,10 @@ intel_info(const struct drm_i915_private *dev_priv) 
#define IS_GEN_RANGE(dev_priv, s, e) \

#define IS_GEN_RANGE(dev_priv, s, e) \

	(!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e))))

	(!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e))))





#define IS_GEN(dev_priv, n) \

	(BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \

	 (dev_priv)->info.gen == (n))



/*

/*

 * Return true if revision is in range [since,until] inclusive.

 * Return true if revision is in range [since,until] inclusive.

 *

 *
@@ -2365,26 +2369,9 @@ intel_info(const struct drm_i915_private *dev_priv) 
#define IS_ICL_REVID(p, since, until) \

#define IS_ICL_REVID(p, since, until) \

	(IS_ICELAKE(p) && IS_REVID(p, since, until))

	(IS_ICELAKE(p) && IS_REVID(p, since, until))





/*

 * The genX designation typically refers to the render engine, so render

 * capability related checks should use IS_GEN, while display and other checks

 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular

 * chips, etc.).

 */

#define IS_GEN2(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(1)))

#define IS_GEN3(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(2)))

#define IS_GEN4(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(3)))

#define IS_GEN5(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(4)))

#define IS_GEN6(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(5)))

#define IS_GEN7(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(6)))

#define IS_GEN8(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(7)))

#define IS_GEN9(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(8)))

#define IS_GEN10(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(9)))

#define IS_GEN11(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(10)))



#define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)

#define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)

#define IS_GEN9_LP(dev_priv)	(IS_GEN9(dev_priv) && IS_LP(dev_priv))

#define IS_GEN9_LP(dev_priv)	(IS_GEN(dev_priv, 9) && IS_LP(dev_priv))

#define IS_GEN9_BC(dev_priv)	(IS_GEN9(dev_priv) && !IS_LP(dev_priv))

#define IS_GEN9_BC(dev_priv)	(IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))





#define ENGINE_MASK(id)	BIT(id)

#define ENGINE_MASK(id)	BIT(id)

#define RENDER_RING	ENGINE_MASK(RCS)

#define RENDER_RING	ENGINE_MASK(RCS)
@@ -2405,7 +2392,7 @@ intel_info(const struct drm_i915_private *dev_priv) 
#define HAS_BLT(dev_priv)	HAS_ENGINE(dev_priv, BCS)

#define HAS_BLT(dev_priv)	HAS_ENGINE(dev_priv, BCS)

#define HAS_VEBOX(dev_priv)	HAS_ENGINE(dev_priv, VECS)

#define HAS_VEBOX(dev_priv)	HAS_ENGINE(dev_priv, VECS)





#define HAS_LEGACY_SEMAPHORES(dev_priv) IS_GEN7(dev_priv)

#define HAS_LEGACY_SEMAPHORES(dev_priv) IS_GEN(dev_priv, 7)





#define HAS_LLC(dev_priv)	((dev_priv)->info.has_llc)

#define HAS_LLC(dev_priv)	((dev_priv)->info.has_llc)

#define HAS_SNOOP(dev_priv)	((dev_priv)->info.has_snoop)

#define HAS_SNOOP(dev_priv)	((dev_priv)->info.has_snoop)
@@ -2457,7 +2444,7 @@ intel_info(const struct drm_i915_private *dev_priv) 
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte

/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte

 * rows, which changed the alignment requirements and fence programming.

 * rows, which changed the alignment requirements and fence programming.

 */

 */

#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \

#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \

					 !(IS_I915G(dev_priv) || \

					 !(IS_I915G(dev_priv) || \

					 IS_I915GM(dev_priv)))

					 IS_I915GM(dev_priv)))

#define SUPPORTS_TV(dev_priv)		((dev_priv)->info.display.supports_tv)

#define SUPPORTS_TV(dev_priv)		((dev_priv)->info.display.supports_tv)