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Commit 00690008 authored Dec 12, 2018 by Lucas De Marchi Committed by Rodrigo Vivi Dec 12, 2018

drm/i915: Rename IS_GEN to IS_GEN_RANGE



RANGE makes it longer, but clearer. We are also going to add a macro to
check an individual gen, so add the _RANGE prefix here.

Diff generated with:

sed 's/IS_GEN(/IS_GEN_RANGE(/g' drivers/gpu/drm/i915/{*/,}*.{c,h} -i

v2: use IS_GEN rather than GT_GEN

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181212181044.15886-1-lucas.demarchi@intel.com

parent 25db2eaf

drivers/gpu/drm/i915/i915_drv.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -2211,7 +2211,7 @@ intel_info(const struct drm_i915_private *dev_priv)
		GENMASK((e) - 1, (s) - 1))

		/* Returns true if Gen is in inclusive range [Start, End] */
		#define IS_GEN(dev_priv, s, e) \
		#define IS_GEN_RANGE(dev_priv, s, e) \
		(!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e))))

		/*

drivers/gpu/drm/i915/i915_perf.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -1796,7 +1796,7 @@ static int gen8_enable_metric_set(struct i915_perf_stream *stream)
		* be read back from automatically triggered reports, as part of the
		* RPT_ID field.
		*/
		if (IS_GEN(dev_priv, 9, 11)) {
		if (IS_GEN_RANGE(dev_priv, 9, 11)) {
		I915_WRITE(GEN8_OA_DEBUG,
		_MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS \|
		GEN9_OA_DEBUG_INCLUDE_CLK_RATIO));
		@@ -3442,7 +3442,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv)

		dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<16);
		}
		} else if (IS_GEN(dev_priv, 10, 11)) {
		} else if (IS_GEN_RANGE(dev_priv, 10, 11)) {
		dev_priv->perf.oa.ops.is_valid_b_counter_reg =
		gen7_is_valid_b_counter_addr;
		dev_priv->perf.oa.ops.is_valid_mux_reg =

drivers/gpu/drm/i915/intel_bios.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -453,7 +453,7 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv, u8 bdb_version)
		* Only parse SDVO mappings on gens that could have SDVO. This isn't
		* accurate and doesn't have to be, as long as it's not too strict.
		*/
		if (!IS_GEN(dev_priv, 3, 7)) {
		if (!IS_GEN_RANGE(dev_priv, 3, 7)) {
		DRM_DEBUG_KMS("Skipping SDVO device mapping\n");
		return;
		}

drivers/gpu/drm/i915/intel_engine_cs.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -1248,7 +1248,7 @@ static void intel_engine_print_registers(const struct intel_engine_cs *engine,
		&engine->execlists;
		u64 addr;

		if (engine->id == RCS && IS_GEN(dev_priv, 4, 7))
		if (engine->id == RCS && IS_GEN_RANGE(dev_priv, 4, 7))
		drm_printf(m, "\tCCID: 0x%08x\n", I915_READ(CCID));
		drm_printf(m, "\tRING_START: 0x%08x\n",
		I915_READ(RING_START(engine->mmio_base)));

drivers/gpu/drm/i915/intel_fbc.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -787,7 +787,7 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
		* having a Y offset that isn't divisible by 4 causes FIFO underrun
		* and screen flicker.
		*/
		if (IS_GEN(dev_priv, 9, 10) &&
		if (IS_GEN_RANGE(dev_priv, 9, 10) &&
		(fbc->state_cache.plane.adjusted_y & 3)) {
		fbc->no_fbc_reason = "plane Y offset is misaligned";
		return false;