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Commit f1b53c4e authored by Mikko Perttunen's avatar Mikko Perttunen Committed by Thierry Reding
Browse files

gpu: host1x: Add Tegra186 support 



Add support for the implementation of Host1x present on the Tegra186.
The register space has been shuffled around a little bit, requiring
addition of some chip-specific code sections. Tegra186 also adds
several new features, most importantly the hypervisor, but those are
not yet supported with this commit.

Signed-off-by: default avatarMikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: default avatarDmitry Osipenko <digetx@gmail.com>
Tested-by: default avatarDmitry Osipenko <digetx@gmail.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent d3b3efa1

drivers/gpu/host1x/Makefile

+2 −1
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ host1x-y = \ 
	hw/host1x01.o \

	hw/host1x02.o \

	hw/host1x04.o \

	hw/host1x05.o

	hw/host1x05.o \

	hw/host1x06.o



obj-$(CONFIG_TEGRA_HOST1X) += host1x.o

drivers/gpu/host1x/dev.c

+50 −5
Original line number Diff line number Diff line
@@ -39,6 +39,17 @@ 
#include "hw/host1x02.h"

#include "hw/host1x04.h"

#include "hw/host1x05.h"

#include "hw/host1x06.h"



void host1x_hypervisor_writel(struct host1x *host1x, u32 v, u32 r)

{

	writel(v, host1x->hv_regs + r);

}



u32 host1x_hypervisor_readl(struct host1x *host1x, u32 r)

{

	return readl(host1x->hv_regs + r);

}



void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r)

{
@@ -104,7 +115,19 @@ static const struct host1x_info host1x05_info = { 
	.dma_mask = DMA_BIT_MASK(34),

};



static const struct host1x_info host1x06_info = {

	.nb_channels = 63,

	.nb_pts = 576,

	.nb_mlocks = 24,

	.nb_bases = 16,

	.init = host1x06_init,

	.sync_offset = 0x0,

	.dma_mask = DMA_BIT_MASK(34),

	.has_hypervisor = true,

};



static const struct of_device_id host1x_of_match[] = {

	{ .compatible = "nvidia,tegra186-host1x", .data = &host1x06_info, },

	{ .compatible = "nvidia,tegra210-host1x", .data = &host1x05_info, },

	{ .compatible = "nvidia,tegra124-host1x", .data = &host1x04_info, },

	{ .compatible = "nvidia,tegra114-host1x", .data = &host1x02_info, },
@@ -117,7 +140,7 @@ MODULE_DEVICE_TABLE(of, host1x_of_match); 
static int host1x_probe(struct platform_device *pdev)

{

	struct host1x *host;

	struct resource *regs;

	struct resource *regs, *hv_regs = NULL;

	int syncpt_irq;

	int err;
@@ -127,11 +150,27 @@ static int host1x_probe(struct platform_device *pdev) 


	host->info = of_device_get_match_data(&pdev->dev);



	if (host->info->has_hypervisor) {

		regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vm");

		if (!regs) {

			dev_err(&pdev->dev, "failed to get vm registers\n");

			return -ENXIO;

		}



		hv_regs = platform_get_resource_byname(pdev, IORESOURCE_MEM,

						       "hypervisor");

		if (!hv_regs) {

			dev_err(&pdev->dev,

				"failed to get hypervisor registers\n");

			return -ENXIO;

		}

	} else {

		regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);

		if (!regs) {

			dev_err(&pdev->dev, "failed to get registers\n");

			return -ENXIO;

		}

	}



	syncpt_irq = platform_get_irq(pdev, 0);

	if (syncpt_irq < 0) {
@@ -151,6 +190,12 @@ static int host1x_probe(struct platform_device *pdev) 
	if (IS_ERR(host->regs))

		return PTR_ERR(host->regs);



	if (host->info->has_hypervisor) {

		host->hv_regs = devm_ioremap_resource(&pdev->dev, hv_regs);

		if (IS_ERR(host->hv_regs))

			return PTR_ERR(host->hv_regs);

	}



	dma_set_mask_and_coherent(host->dev, host->info->dma_mask);



	if (host->info->init) {

drivers/gpu/host1x/dev.h

+4 −0
Original line number Diff line number Diff line
@@ -100,12 +100,14 @@ struct host1x_info { 
	int (*init)(struct host1x *host1x); /* initialize per SoC ops */

	unsigned int sync_offset; /* offset of syncpoint registers */

	u64 dma_mask; /* mask of addressable memory */

	bool has_hypervisor; /* has hypervisor registers */

};



struct host1x {

	const struct host1x_info *info;



	void __iomem *regs;

	void __iomem *hv_regs; /* hypervisor region */

	struct host1x_syncpt *syncpt;

	struct host1x_syncpt_base *bases;

	struct device *dev;
@@ -140,6 +142,8 @@ struct host1x { 
	struct list_head list;

};



void host1x_hypervisor_writel(struct host1x *host1x, u32 r, u32 v);

u32 host1x_hypervisor_readl(struct host1x *host1x, u32 r);

void host1x_sync_writel(struct host1x *host1x, u32 r, u32 v);

u32 host1x_sync_readl(struct host1x *host1x, u32 r);

void host1x_ch_writel(struct host1x_channel *ch, u32 r, u32 v);

drivers/gpu/host1x/hw/cdma_hw.c

+30 −19
Original line number Diff line number Diff line
@@ -172,6 +172,30 @@ static void cdma_stop(struct host1x_cdma *cdma) 
	mutex_unlock(&cdma->lock);

}



static void cdma_hw_cmdproc_stop(struct host1x *host, struct host1x_channel *ch,

				 bool stop)

{

#if HOST1X_HW >= 6

	host1x_ch_writel(ch, stop ? 0x1 : 0x0, HOST1X_CHANNEL_CMDPROC_STOP);

#else

	u32 cmdproc_stop = host1x_sync_readl(host, HOST1X_SYNC_CMDPROC_STOP);

	if (stop)

		cmdproc_stop |= BIT(ch->id);

	else

		cmdproc_stop &= ~BIT(ch->id);

	host1x_sync_writel(host, cmdproc_stop, HOST1X_SYNC_CMDPROC_STOP);

#endif

}



static void cdma_hw_teardown(struct host1x *host, struct host1x_channel *ch)

{

#if HOST1X_HW >= 6

	host1x_ch_writel(ch, 0x1, HOST1X_CHANNEL_TEARDOWN);

#else

	host1x_sync_writel(host, BIT(ch->id), HOST1X_SYNC_CH_TEARDOWN);

#endif

}



/*

 * Stops both channel's command processor and CDMA immediately.

 * Also, tears down the channel and resets corresponding module.
@@ -180,7 +204,6 @@ static void cdma_freeze(struct host1x_cdma *cdma) 
{

	struct host1x *host = cdma_to_host1x(cdma);

	struct host1x_channel *ch = cdma_to_channel(cdma);

	u32 cmdproc_stop;



	if (cdma->torndown && !cdma->running) {

		dev_warn(host->dev, "Already torn down\n");
@@ -189,9 +212,7 @@ static void cdma_freeze(struct host1x_cdma *cdma) 


	dev_dbg(host->dev, "freezing channel (id %d)\n", ch->id);



	cmdproc_stop = host1x_sync_readl(host, HOST1X_SYNC_CMDPROC_STOP);

	cmdproc_stop |= BIT(ch->id);

	host1x_sync_writel(host, cmdproc_stop, HOST1X_SYNC_CMDPROC_STOP);

	cdma_hw_cmdproc_stop(host, ch, true);



	dev_dbg(host->dev, "%s: DMA GET 0x%x, PUT HW 0x%x / shadow 0x%x\n",

		__func__, host1x_ch_readl(ch, HOST1X_CHANNEL_DMAGET),
@@ -201,7 +222,7 @@ static void cdma_freeze(struct host1x_cdma *cdma) 
	host1x_ch_writel(ch, HOST1X_CHANNEL_DMACTRL_DMASTOP,

			 HOST1X_CHANNEL_DMACTRL);



	host1x_sync_writel(host, BIT(ch->id), HOST1X_SYNC_CH_TEARDOWN);

	cdma_hw_teardown(host, ch);



	cdma->running = false;

	cdma->torndown = true;
@@ -211,15 +232,12 @@ static void cdma_resume(struct host1x_cdma *cdma, u32 getptr) 
{

	struct host1x *host1x = cdma_to_host1x(cdma);

	struct host1x_channel *ch = cdma_to_channel(cdma);

	u32 cmdproc_stop;



	dev_dbg(host1x->dev,

		"resuming channel (id %u, DMAGET restart = 0x%x)\n",

		ch->id, getptr);



	cmdproc_stop = host1x_sync_readl(host1x, HOST1X_SYNC_CMDPROC_STOP);

	cmdproc_stop &= ~BIT(ch->id);

	host1x_sync_writel(host1x, cmdproc_stop, HOST1X_SYNC_CMDPROC_STOP);

	cdma_hw_cmdproc_stop(host1x, ch, false);



	cdma->torndown = false;

	cdma_timeout_restart(cdma, getptr);
@@ -232,7 +250,7 @@ static void cdma_resume(struct host1x_cdma *cdma, u32 getptr) 
 */

static void cdma_timeout_handler(struct work_struct *work)

{

	u32 prev_cmdproc, cmdproc_stop, syncpt_val;

	u32 syncpt_val;

	struct host1x_cdma *cdma;

	struct host1x *host1x;

	struct host1x_channel *ch;
@@ -254,12 +272,7 @@ static void cdma_timeout_handler(struct work_struct *work) 
	}



	/* stop processing to get a clean snapshot */

	prev_cmdproc = host1x_sync_readl(host1x, HOST1X_SYNC_CMDPROC_STOP);

	cmdproc_stop = prev_cmdproc | BIT(ch->id);

	host1x_sync_writel(host1x, cmdproc_stop, HOST1X_SYNC_CMDPROC_STOP);



	dev_dbg(host1x->dev, "cdma_timeout: cmdproc was 0x%x is 0x%x\n",

		prev_cmdproc, cmdproc_stop);

	cdma_hw_cmdproc_stop(host1x, ch, true);



	syncpt_val = host1x_syncpt_load(cdma->timeout.syncpt);
@@ -268,9 +281,7 @@ static void cdma_timeout_handler(struct work_struct *work) 
		dev_dbg(host1x->dev,

			"cdma_timeout: expired, but buffer had completed\n");

		/* restore */

		cmdproc_stop = prev_cmdproc & ~(BIT(ch->id));

		host1x_sync_writel(host1x, cmdproc_stop,

				   HOST1X_SYNC_CMDPROC_STOP);

		cdma_hw_cmdproc_stop(host1x, ch, false);

		mutex_unlock(&cdma->lock);

		return;

	}

drivers/gpu/host1x/hw/debug_hw.c

+5 −132
Original line number Diff line number Diff line
@@ -174,138 +174,11 @@ static void show_channel_gathers(struct output *o, struct host1x_cdma *cdma) 
	}

}



static void host1x_debug_show_channel_cdma(struct host1x *host,

					   struct host1x_channel *ch,

					   struct output *o)

{

	struct host1x_cdma *cdma = &ch->cdma;

	u32 dmaput, dmaget, dmactrl;

	u32 cbstat, cbread;

	u32 val, base, baseval;



	dmaput = host1x_ch_readl(ch, HOST1X_CHANNEL_DMAPUT);

	dmaget = host1x_ch_readl(ch, HOST1X_CHANNEL_DMAGET);

	dmactrl = host1x_ch_readl(ch, HOST1X_CHANNEL_DMACTRL);

	cbread = host1x_sync_readl(host, HOST1X_SYNC_CBREAD(ch->id));

	cbstat = host1x_sync_readl(host, HOST1X_SYNC_CBSTAT(ch->id));



	host1x_debug_output(o, "%u-%s: ", ch->id, dev_name(ch->dev));



	if (HOST1X_CHANNEL_DMACTRL_DMASTOP_V(dmactrl) ||

	    !ch->cdma.push_buffer.mapped) {

		host1x_debug_output(o, "inactive\n\n");

		return;

	}



	if (HOST1X_SYNC_CBSTAT_CBCLASS_V(cbstat) == HOST1X_CLASS_HOST1X &&

	    HOST1X_SYNC_CBSTAT_CBOFFSET_V(cbstat) ==

			HOST1X_UCLASS_WAIT_SYNCPT)

		host1x_debug_output(o, "waiting on syncpt %d val %d\n",

				    cbread >> 24, cbread & 0xffffff);

	else if (HOST1X_SYNC_CBSTAT_CBCLASS_V(cbstat) ==

				HOST1X_CLASS_HOST1X &&

		 HOST1X_SYNC_CBSTAT_CBOFFSET_V(cbstat) ==

				HOST1X_UCLASS_WAIT_SYNCPT_BASE) {

		base = (cbread >> 16) & 0xff;

		baseval =

			host1x_sync_readl(host, HOST1X_SYNC_SYNCPT_BASE(base));

		val = cbread & 0xffff;

		host1x_debug_output(o, "waiting on syncpt %d val %d (base %d = %d; offset = %d)\n",

				    cbread >> 24, baseval + val, base,

				    baseval, val);

	} else

		host1x_debug_output(o, "active class %02x, offset %04x, val %08x\n",

				    HOST1X_SYNC_CBSTAT_CBCLASS_V(cbstat),

				    HOST1X_SYNC_CBSTAT_CBOFFSET_V(cbstat),

				    cbread);



	host1x_debug_output(o, "DMAPUT %08x, DMAGET %08x, DMACTL %08x\n",

			    dmaput, dmaget, dmactrl);

	host1x_debug_output(o, "CBREAD %08x, CBSTAT %08x\n", cbread, cbstat);



	show_channel_gathers(o, cdma);

	host1x_debug_output(o, "\n");

}



static void host1x_debug_show_channel_fifo(struct host1x *host,

					   struct host1x_channel *ch,

					   struct output *o)

{

	u32 val, rd_ptr, wr_ptr, start, end;

	unsigned int data_count = 0;



	host1x_debug_output(o, "%u: fifo:\n", ch->id);



	val = host1x_ch_readl(ch, HOST1X_CHANNEL_FIFOSTAT);

	host1x_debug_output(o, "FIFOSTAT %08x\n", val);

	if (HOST1X_CHANNEL_FIFOSTAT_CFEMPTY_V(val)) {

		host1x_debug_output(o, "[empty]\n");

		return;

	}



	host1x_sync_writel(host, 0x0, HOST1X_SYNC_CFPEEK_CTRL);

	host1x_sync_writel(host, HOST1X_SYNC_CFPEEK_CTRL_ENA_F(1) |

			   HOST1X_SYNC_CFPEEK_CTRL_CHANNR_F(ch->id),

			   HOST1X_SYNC_CFPEEK_CTRL);



	val = host1x_sync_readl(host, HOST1X_SYNC_CFPEEK_PTRS);

	rd_ptr = HOST1X_SYNC_CFPEEK_PTRS_CF_RD_PTR_V(val);

	wr_ptr = HOST1X_SYNC_CFPEEK_PTRS_CF_WR_PTR_V(val);



	val = host1x_sync_readl(host, HOST1X_SYNC_CF_SETUP(ch->id));

	start = HOST1X_SYNC_CF_SETUP_BASE_V(val);

	end = HOST1X_SYNC_CF_SETUP_LIMIT_V(val);



	do {

		host1x_sync_writel(host, 0x0, HOST1X_SYNC_CFPEEK_CTRL);

		host1x_sync_writel(host, HOST1X_SYNC_CFPEEK_CTRL_ENA_F(1) |

				   HOST1X_SYNC_CFPEEK_CTRL_CHANNR_F(ch->id) |

				   HOST1X_SYNC_CFPEEK_CTRL_ADDR_F(rd_ptr),

				   HOST1X_SYNC_CFPEEK_CTRL);

		val = host1x_sync_readl(host, HOST1X_SYNC_CFPEEK_READ);



		if (!data_count) {

			host1x_debug_output(o, "%08x:", val);

			data_count = show_channel_command(o, val);

		} else {

			host1x_debug_output(o, "%08x%s", val,

					    data_count > 0 ? ", " : "])\n");

			data_count--;

		}



		if (rd_ptr == end)

			rd_ptr = start;

		else

			rd_ptr++;

	} while (rd_ptr != wr_ptr);



	if (data_count)

		host1x_debug_output(o, ", ...])\n");

	host1x_debug_output(o, "\n");



	host1x_sync_writel(host, 0x0, HOST1X_SYNC_CFPEEK_CTRL);

}



static void host1x_debug_show_mlocks(struct host1x *host, struct output *o)

{

	unsigned int i;



	host1x_debug_output(o, "---- mlocks ----\n");



	for (i = 0; i < host1x_syncpt_nb_mlocks(host); i++) {

		u32 owner =

			host1x_sync_readl(host, HOST1X_SYNC_MLOCK_OWNER(i));

		if (HOST1X_SYNC_MLOCK_OWNER_CH_OWNS_V(owner))

			host1x_debug_output(o, "%u: locked by channel %u\n",

				i, HOST1X_SYNC_MLOCK_OWNER_CHID_V(owner));

		else if (HOST1X_SYNC_MLOCK_OWNER_CPU_OWNS_V(owner))

			host1x_debug_output(o, "%u: locked by cpu\n", i);

		else

			host1x_debug_output(o, "%u: unlocked\n", i);

	}



	host1x_debug_output(o, "\n");

}

#if HOST1X_HW >= 6

#include "debug_hw_1x06.c"

#else

#include "debug_hw_1x01.c"

#endif



static const struct host1x_debug_ops host1x_debug_ops = {

	.show_channel_cdma = host1x_debug_show_channel_cdma,