dwc3-msm: Add support to vote USB FORCE_MEM_CORE_ON

USB FORCE_MEM_CORE_ON is need to set 1 with GCC_USB30_MASTER_CLK to
retain USB controller CSR when system is into CXPC (i.e. using MX
instead of CX). Without this bit set, USB controller CSR is not
retain once coming out of CXPC. Add support to vote this as clock
and tie with USB GDSC functionality.

Change-Id: I25e65a2d06848ef84ec5fd2041db8c6a8d9a7b4e
Signed-off-by: Mayank Rana <mrana@codeaurora.org>