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Commit f150097f authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "ARM: dts: msm: Update QMP Phy init sequence for Lahaina to v1.09"

parents 94fad7e9 15e6d83b

qcom/lahaina-usb.dtsi

+10 −4
Original line number Diff line number Diff line
@@ -224,6 +224,7 @@ 
			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x16 0

			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x0E 0

			USB3_DP_QSERDES_TXA_LANE_MODE_1 0x35 0

			USB3_DP_QSERDES_TXA_LANE_MODE_3 0x3F 0

			USB3_DP_QSERDES_TXA_LANE_MODE_4 0x7F 0

			USB3_DP_QSERDES_TXA_LANE_MODE_5 0x3F 0

			USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12 0
@@ -254,8 +255,8 @@ 
			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0xBB 0

			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x3D 0

			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0xDB 0

			USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0x5B 0

			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0x1B 0

			USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0x64 0

			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0x24 0

			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0xD2 0

			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x13 0

			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0xA9 0
@@ -270,6 +271,7 @@ 
			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x16 0

			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x0E 0

			USB3_DP_QSERDES_TXB_LANE_MODE_1 0x35 0

			USB3_DP_QSERDES_TXB_LANE_MODE_3 0x3F 0

			USB3_DP_QSERDES_TXB_LANE_MODE_4 0x7F 0

			USB3_DP_QSERDES_TXB_LANE_MODE_5 0x3F 0

			USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12 0
@@ -300,8 +302,8 @@ 
			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0xBB 0

			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x3C 0

			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0xDB 0

			USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0x5B 0

			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0x1B 0

			USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0x64 0

			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0x24 0

			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0xD2 0

			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x13 0

			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0xA9 0
@@ -310,6 +312,10 @@ 
			USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0xA0 0

			USB3_DP_QSERDES_RXB_DCC_CTRL1 0x0C 0

			USB3_DP_QSERDES_RXB_GM_CAL 0x00 0

			USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40 0

			USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x00 0

			USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_L 0xE7 0

			USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 0

			USB3_DP_QSERDES_RXB_VTH_CODE 0x10 0

			USB3_DP_PCS_LOCK_DETECT_CONFIG1 0xD0 0

			USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x07 0