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Commit ef3efce5 authored by Tony Truong's avatar Tony Truong
Browse files

msm: pcie: add support to control pipe clk mux for LPM 



PCIe driver needs to toggle between bi_tcxo and phy pipe
clock as part of its LPM sequence. This is done by setting
pipe_clk/ref_clk_src as parent of pipe_clk_src.

Change-Id: Ie634e6024fef3e5736793fc53d281be2d52bcbf7
Signed-off-by: default avatarTony Truong <truong@codeaurora.org>
parent 1b9adac1

drivers/pci/controller/pci-msm.c

+42 −4
Original line number Diff line number Diff line
@@ -167,7 +167,7 @@ 
#define MAX_PROP_SIZE (32)

#define MAX_RC_NAME_LEN (15)

#define MSM_PCIE_MAX_VREG (4)

#define MSM_PCIE_MAX_CLK (16)

#define MSM_PCIE_MAX_CLK (18)

#define MSM_PCIE_MAX_PIPE_CLK (1)

#define MAX_RC_NUM (3)

#define MAX_DEVICE_NUM (20)
@@ -655,6 +655,10 @@ struct msm_pcie_dev_t { 
	struct msm_pcie_bw_scale_info_t *bw_scale;

	u32 bw_gen_max;



	struct clk *pipe_clk_mux;

	struct clk *pipe_clk_ext_src;

	struct clk *ref_clk_src;



	bool cfg_access;

	spinlock_t cfg_lock;

	unsigned long irqsave_flags;
@@ -861,7 +865,9 @@ static struct msm_pcie_clk_info_t 
	{NULL, "pcie_aggre_noc_0_axi_clk", 0, false, false},

	{NULL, "pcie_aggre_noc_1_axi_clk", 0, false, false},

	{NULL, "pcie_phy_cfg_ahb_clk", 0, false, false},

	{NULL, "pcie_phy_aux_clk", 0, false, false}

	{NULL, "pcie_phy_aux_clk", 0, false, false},

	{NULL, "pcie_pipe_clk_mux", 0, false, false},

	{NULL, "pcie_pipe_clk_ext_src", 0, false, false}

	},

	{

	{NULL, "pcie_1_ref_clk_src", 0, false, false},
@@ -879,7 +885,9 @@ static struct msm_pcie_clk_info_t 
	{NULL, "pcie_aggre_noc_1_axi_clk", 0, false, false},

	{NULL, "pcie_ddrss_sf_tbu_clk", 0, false, true},

	{NULL, "pcie_phy_cfg_ahb_clk", 0, false, false},

	{NULL, "pcie_phy_aux_clk", 0, false, false}

	{NULL, "pcie_phy_aux_clk", 0, false, false},

	{NULL, "pcie_pipe_clk_mux", 0, false, false},

	{NULL, "pcie_pipe_clk_ext_src", 0, false, false}

	},

	{

	{NULL, "pcie_2_ref_clk_src", 0, false, false},
@@ -897,7 +905,9 @@ static struct msm_pcie_clk_info_t 
	{NULL, "pcie_aggre_noc_1_axi_clk", 0, false, false},

	{NULL, "pcie_ddrss_sf_tbu_clk", 0, false, true},

	{NULL, "pcie_phy_cfg_ahb_clk", 0, false, false},

	{NULL, "pcie_phy_aux_clk", 0, false, false}

	{NULL, "pcie_phy_aux_clk", 0, false, false},

	{NULL, "pcie_pipe_clk_mux", 0, false, false},

	{NULL, "pcie_pipe_clk_ext_src", 0, false, false}

	}

};
@@ -3087,6 +3097,10 @@ static int msm_pcie_clk_init(struct msm_pcie_dev_t *dev) 
		return rc;

	}



	/* switch pipe clock source after gdsc is turned on */

	if (dev->pipe_clk_mux && dev->pipe_clk_ext_src)

		clk_set_parent(dev->pipe_clk_mux, dev->pipe_clk_ext_src);



	if (dev->icc_path) {

		PCIE_DBG(dev, "PCIe: RC%d: setting ICC path vote\n",

			dev->rc_idx);
@@ -3150,6 +3164,10 @@ static int msm_pcie_clk_init(struct msm_pcie_dev_t *dev) 
		}



		regulator_disable(dev->gdsc);



		/* switch pipe clock mux after gdsc is turned off */

		if (dev->pipe_clk_mux && dev->ref_clk_src)

			clk_set_parent(dev->pipe_clk_mux, dev->ref_clk_src);

	}



	for (i = 0; i < MSM_PCIE_MAX_RESET; i++) {
@@ -3224,6 +3242,10 @@ static void msm_pcie_clk_deinit(struct msm_pcie_dev_t *dev) 


	regulator_disable(dev->gdsc);



	/* switch pipe clock mux after gdsc is turned off */

	if (dev->pipe_clk_mux && dev->ref_clk_src)

		clk_set_parent(dev->pipe_clk_mux, dev->ref_clk_src);



	PCIE_DBG(dev, "RC%d: exit\n", dev->rc_idx);

}
@@ -3473,6 +3495,7 @@ static int msm_pcie_get_clk(struct msm_pcie_dev_t *pcie_dev) 
	struct msm_pcie_clk_info_t *clk_info;

	u32 *clkfreq = NULL;

	struct platform_device *pdev = pcie_dev->pdev;

	char ref_clk_src[MAX_PROP_SIZE];



	cnt = of_property_count_elems_of_size((&pdev->dev)->of_node,

			"max-clock-frequency-hz", sizeof(u32));
@@ -3519,6 +3542,21 @@ static int msm_pcie_get_clk(struct msm_pcie_dev_t *pcie_dev) 
		}

	}



	pcie_dev->pipe_clk_mux = clk_get(&pdev->dev, "pcie_pipe_clk_mux");

	if (IS_ERR(pcie_dev->pipe_clk_mux))

		pcie_dev->pipe_clk_mux = NULL;



	pcie_dev->pipe_clk_ext_src = clk_get(&pdev->dev,

					"pcie_pipe_clk_ext_src");

	if (IS_ERR(pcie_dev->pipe_clk_ext_src))

		pcie_dev->pipe_clk_ext_src = NULL;



	scnprintf(ref_clk_src, MAX_PROP_SIZE, "pcie_%d_ref_clk_src",

		pcie_dev->rc_idx);

	pcie_dev->ref_clk_src = clk_get(&pdev->dev, ref_clk_src);

	if (IS_ERR(pcie_dev->ref_clk_src))

		pcie_dev->ref_clk_src = NULL;



	for (i = 0; i < MSM_PCIE_MAX_PIPE_CLK; i++) {

		clk_info = &pcie_dev->pipeclk[i];