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Commit ee63b78d authored by Manuel Gomez's avatar Manuel Gomez
Browse files

ARM: dts: msm: Pin config for AQR and Napa INTN_WOL 

Enable pin control for qps615 that is necessary to configure
the SDX65 GPIO pins for Wake on LAN support.

Change-Id: Ic5d6d76677e195fc3dec7780d99b5cf50718b8b1
parent 8dc5a38b

qcom/sdxlemur-mtp-cpe.dtsi

+6 −0
Original line number Diff line number Diff line
@@ -139,6 +139,9 @@ 
			qps615_eth0,qps615_eth0@pcie0_rp {

				reg = <0x0 0x0 0x0 0x0 0x0>;



				pinctrl-names = "default";

				pinctrl-0 = <&aqr_intn_wol_sig>;



				compatible = "qcom,ioss-v2-device";

				qcom,ioss = <&ioss>;

				qcom,ioss_interfaces = <&ioss_qps615_eth0>;
@@ -161,6 +164,9 @@ 
			qps615_eth1,qps615_eth1@pcie0_rp {

				reg = <0x100 0x0 0x0 0x0 0x0>;



				pinctrl-names = "default";

				pinctrl-0 = <&napa_intn_wol_sig>;



				compatible = "qcom,ioss-v2-device";

				qcom,ioss = <&ioss>;

				qcom,ioss_interfaces = <&ioss_qps615_eth1>;

qcom/sdxlemur-pinctrl.dtsi

+28 −0
Original line number Diff line number Diff line
@@ -1699,5 +1699,33 @@ 
				};

			};

		};



		qps615_intn_wol {

			aqr_intn_wol_sig: aqr_intn_wol_sig {

				mux {

					pins = "gpio103";

					function = "gpio";

				};



				config {

					pins = "gpio103";

					input-enable;

					bias-disable;

				};

			};



			napa_intn_wol_sig: napa_intn_wol_sig {

				mux {

					pins = "gpio81";

					function = "gpio";

				};



				config {

					pins = "gpio81";

					input-enable;

					bias-disable;

				};

			};

		};

	};

};