Loading qcom/lahaina.dtsi +8 −0 Original line number Diff line number Diff line Loading @@ -2154,6 +2154,7 @@ reg = <0x7040000 0x1000>; reg-names = "etm-base"; status = "disabled"; clocks = <&clock_aop QDSS_CLK>; clock-names = "core_clk"; Loading @@ -2165,6 +2166,7 @@ reg = <0x7140000 0x1000>; reg-names = "etm-base"; status = "disabled"; clocks = <&clock_aop QDSS_CLK>; clock-names = "core_clk"; Loading @@ -2176,6 +2178,7 @@ reg = <0x7240000 0x1000>; reg-names = "etm-base"; status = "disabled"; clocks = <&clock_aop QDSS_CLK>; clock-names = "core_clk"; Loading @@ -2187,6 +2190,7 @@ reg = <0x7340000 0x1000>; reg-names = "etm-base"; status = "disabled"; clocks = <&clock_aop QDSS_CLK>; clock-names = "core_clk"; Loading @@ -2198,6 +2202,7 @@ reg = <0x7440000 0x1000>; reg-names = "etm-base"; status = "disabled"; clocks = <&clock_aop QDSS_CLK>; clock-names = "core_clk"; Loading @@ -2209,6 +2214,7 @@ reg = <0x7540000 0x1000>; reg-names = "etm-base"; status = "disabled"; clocks = <&clock_aop QDSS_CLK>; clock-names = "core_clk"; Loading @@ -2220,6 +2226,7 @@ reg = <0x7640000 0x1000>; reg-names = "etm-base"; status = "disabled"; clocks = <&clock_aop QDSS_CLK>; clock-names = "core_clk"; Loading @@ -2231,6 +2238,7 @@ reg = <0x7740000 0x1000>; reg-names = "etm-base"; status = "disabled"; clocks = <&clock_aop QDSS_CLK>; clock-names = "core_clk"; Loading Loading
qcom/lahaina.dtsi +8 −0 Original line number Diff line number Diff line Loading @@ -2154,6 +2154,7 @@ reg = <0x7040000 0x1000>; reg-names = "etm-base"; status = "disabled"; clocks = <&clock_aop QDSS_CLK>; clock-names = "core_clk"; Loading @@ -2165,6 +2166,7 @@ reg = <0x7140000 0x1000>; reg-names = "etm-base"; status = "disabled"; clocks = <&clock_aop QDSS_CLK>; clock-names = "core_clk"; Loading @@ -2176,6 +2178,7 @@ reg = <0x7240000 0x1000>; reg-names = "etm-base"; status = "disabled"; clocks = <&clock_aop QDSS_CLK>; clock-names = "core_clk"; Loading @@ -2187,6 +2190,7 @@ reg = <0x7340000 0x1000>; reg-names = "etm-base"; status = "disabled"; clocks = <&clock_aop QDSS_CLK>; clock-names = "core_clk"; Loading @@ -2198,6 +2202,7 @@ reg = <0x7440000 0x1000>; reg-names = "etm-base"; status = "disabled"; clocks = <&clock_aop QDSS_CLK>; clock-names = "core_clk"; Loading @@ -2209,6 +2214,7 @@ reg = <0x7540000 0x1000>; reg-names = "etm-base"; status = "disabled"; clocks = <&clock_aop QDSS_CLK>; clock-names = "core_clk"; Loading @@ -2220,6 +2226,7 @@ reg = <0x7640000 0x1000>; reg-names = "etm-base"; status = "disabled"; clocks = <&clock_aop QDSS_CLK>; clock-names = "core_clk"; Loading @@ -2231,6 +2238,7 @@ reg = <0x7740000 0x1000>; reg-names = "etm-base"; status = "disabled"; clocks = <&clock_aop QDSS_CLK>; clock-names = "core_clk"; Loading