Loading qcom/shima-rumi.dtsi +5 −0 Original line number Diff line number Diff line Loading @@ -102,3 +102,8 @@ &gcc { clocks = <&bi_tcxo>, <&bi_tcxo_ao>, <&sleep_clk>; }; &aopcc { compatible = "qcom,dummycc"; clock-output-names = "qdss_clocks"; }; qcom/shima.dtsi +3 −3 Original line number Diff line number Diff line Loading @@ -570,10 +570,10 @@ }; aopcc: qcom,aopcc { compatible = "qcom,dummycc"; clock-output-names = "aopcc_clocks"; compatible = "qcom,aop-qmp-clk"; mboxes = <&qmp_aop 0>; mbox-names = "qdss_clk"; #clock-cells = <1>; #reset-cells = <1>; }; gcc: clock-controller@100000 { Loading Loading
qcom/shima-rumi.dtsi +5 −0 Original line number Diff line number Diff line Loading @@ -102,3 +102,8 @@ &gcc { clocks = <&bi_tcxo>, <&bi_tcxo_ao>, <&sleep_clk>; }; &aopcc { compatible = "qcom,dummycc"; clock-output-names = "qdss_clocks"; };
qcom/shima.dtsi +3 −3 Original line number Diff line number Diff line Loading @@ -570,10 +570,10 @@ }; aopcc: qcom,aopcc { compatible = "qcom,dummycc"; clock-output-names = "aopcc_clocks"; compatible = "qcom,aop-qmp-clk"; mboxes = <&qmp_aop 0>; mbox-names = "qdss_clk"; #clock-cells = <1>; #reset-cells = <1>; }; gcc: clock-controller@100000 { Loading