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Commit e72cf798 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: add PMIC devices for SCSHRIKE"

parents 10e2f294 48d59871

qcom/pm8195.dtsi

0 → 100644
+307 −0
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#include <dt-bindings/clock/qcom,rpmh.h>

#include <dt-bindings/iio/qcom,spmi-vadc.h>

#include <dt-bindings/input/input.h>

#include <dt-bindings/input/qcom,qpnp-power-on.h>

#include <dt-bindings/interrupt-controller/irq.h>

#include <dt-bindings/spmi/spmi.h>



&spmi_bus {

	#address-cells = <2>;

	#size-cells = <0>;

	interrupt-controller;

	#interrupt-cells = <4>;



	qcom,pm8195@0 {

		compatible = "qcom,spmi-pmic";

		reg = <0 SPMI_USID>;

		#address-cells = <1>;

		#size-cells = <0>;



		pm8195_1_tz: qcom,temp-alarm@2400 {

			compatible = "qcom,spmi-temp-alarm";

			reg = <0x2400>;

			interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;

			io-channels = <&pm8195_1_vadc ADC5_DIE_TEMP>;

			io-channel-names = "thermal";

			#thermal-sensor-cells = <0>;

			qcom,temperature-threshold-set = <1>;

		};



		pm8195_1_vadc: vadc@3100 {

			compatible = "qcom,spmi-adc5";

			reg = <0x3100>;

			#address-cells = <1>;

			#size-cells = <0>;

			interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;

			interrupt-names = "eoc-int-en-set";

			#io-channel-cells = <1>;

			io-channel-ranges;



			/* Channel node */

			ref_gnd {

				reg = <ADC5_REF_GND>;

				label = "ref_gnd";

				qcom,pre-scaling = <1 1>;

			};



			vref_1p25 {

				reg = <ADC5_1P25VREF>;

				label = "vref_1p25";

				qcom,pre-scaling = <1 1>;

			};



			die_temp {

				reg = <ADC5_DIE_TEMP>;

				label = "die_temp";

				qcom,pre-scaling = <1 1>;

			};

		};



		qcom,power-on@800 {

			compatible = "qcom,qpnp-power-on";

			reg = <0x800>;

			interrupts = <0x0 0x8 0x0 IRQ_TYPE_NONE>,

				     <0x0 0x8 0x1 IRQ_TYPE_NONE>;

			interrupt-names = "kpdpwr", "resin";

			qcom,pon-dbc-delay = <15625>;

			qcom,kpdpwr-sw-debounce;

			qcom,system-reset;

			qcom,store-hard-reset-reason;



			qcom,pon_1 {

				qcom,pon-type = <PON_POWER_ON_TYPE_KPDPWR>;

				qcom,pull-up;

				linux,code = <KEY_POWER>;

			};



			qcom,pon_2 {

				qcom,pon-type = <PON_POWER_ON_TYPE_RESIN>;

				qcom,pull-up;

				linux,code = <KEY_VOLUMEDOWN>;

			};

		};



		pm8195_1_clkdiv: clock-controller@5b00 {

			compatible = "qcom,spmi-clkdiv";

			reg = <0x5b00>;

			#clock-cells = <1>;

			qcom,num-clkdivs = <2>;

			clock-output-names = "pm8195_1_div_clk1",

						"pm8195_1_div_clk2";

			clocks = <&rpmhcc RPMH_CXO_CLK>;

			clock-names = "xo";

		};



		pm8195_1_rtc: qcom,pm8195_1_rtc {

			compatible = "qcom,pm8941-rtc";

			reg = <0x6000>, <0x6100>;

			reg-names = "rtc", "alarm";

			interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;

		};



		pm8195_1_gpios: pinctrl@c000 {

			compatible = "qcom,pm8150-gpio";

			reg = <0xc000>;

			gpio-controller;

			#gpio-cells = <2>;

			interrupt-controller;

			#interrupt-cells = <2>;

		};



		pm8195_1_sdam_2: sdam@b100 {

			compatible = "qcom,spmi-sdam";

			reg = <0xb100>;

		};



	};



	qcom,pm8195@1 {

		compatible ="qcom,spmi-pmic";

		reg = <1 SPMI_USID>;

		#address-cells = <2>;

		#size-cells = <0>;

	};



	/* below definitions are for the second instance of pm8195 */

	qcom,pm8195@4 {

		compatible = "qcom,spmi-pmic";

		reg = <4 SPMI_USID>;

		#address-cells = <1>;

		#size-cells = <0>;



		pm8195_2_tz: qcom,temp-alarm@2400 {

			compatible = "qcom,spmi-temp-alarm";

			reg = <0x2400>;

			interrupts = <0x4 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;

			io-channels = <&pm8195_2_vadc ADC5_DIE_TEMP>;

			io-channel-names = "thermal";

			#thermal-sensor-cells = <0>;

			qcom,temperature-threshold-set = <1>;

		};



		pm8195_2_vadc: vadc@3100 {

			compatible = "qcom,spmi-adc5";

			reg = <0x3100>;

			#address-cells = <1>;

			#size-cells = <0>;

			interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>;

			interrupt-names = "eoc-int-en-set";

			#io-channel-cells = <1>;

			io-channel-ranges;



			/* Channel node */

			ref_gnd {

				reg = <ADC5_REF_GND>;

				label = "ref_gnd";

				qcom,pre-scaling = <1 1>;

			};



			vref_1p25 {

				reg = <ADC5_1P25VREF>;

				label = "vref_1p25";

				qcom,pre-scaling = <1 1>;

			};



			die_temp {

				reg = <ADC5_DIE_TEMP>;

				label = "die_temp";

				qcom,pre-scaling = <1 1>;

			};

		};



		qcom,power-on@800 {

			compatible = "qcom,qpnp-power-on";

			reg = <0x800>;

		};



		pm8195_2_clkdiv: clock-controller@5b00 {

			compatible = "qcom,spmi-clkdiv";

			reg = <0x5b00>;

			#clock-cells = <1>;

			qcom,num-clkdivs = <2>;

			clock-output-names = "pm8195_2_div_clk1",

						"pm8195_2_div_clk2";

			clocks = <&rpmhcc RPMH_CXO_CLK>;

			clock-names = "xo";

		};



		pm8195_2_gpios: pinctrl@c000 {

			compatible = "qcom,pm8150-gpio";

			reg = <0xc000>;

			gpio-controller;

			#gpio-cells = <2>;

			interrupt-controller;

			#interrupt-cells = <2>;

		};

	};



	qcom,pm8195@5 {

		compatible ="qcom,spmi-pmic";

		reg = <5 SPMI_USID>;

		#address-cells = <1>;

		#size-cells = <1>;

	};



	/* below definitions are for the third instance of pm8195 */

	qcom,pm8195@8 {

		compatible = "qcom,spmi-pmic";

		reg = <8 SPMI_USID>;

		#address-cells = <1>;

		#size-cells = <0>;



		pm8195_3_tz: qcom,temp-alarm@2400 {

			compatible = "qcom,spmi-temp-alarm";

			reg = <0x2400>;

			interrupts = <0x8 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;

			io-channels = <&pm8195_3_vadc ADC5_DIE_TEMP>;

			io-channel-names = "thermal";

			#thermal-sensor-cells = <0>;

			qcom,temperature-threshold-set = <1>;

		};



		pm8195_3_vadc: vadc@3100 {

			compatible = "qcom,spmi-adc5";

			reg = <0x3100>;

			#address-cells = <1>;

			#size-cells = <0>;

			interrupts = <0x8 0x31 0x0 IRQ_TYPE_EDGE_RISING>;

			interrupt-names = "eoc-int-en-set";

			#io-channel-cells = <1>;

			io-channel-ranges;



			/* Channel node */

			ref_gnd {

				reg = <ADC5_REF_GND>;

				label = "ref_gnd";

				qcom,pre-scaling = <1 1>;

			};



			vref_1p25 {

				reg = <ADC5_1P25VREF>;

				label = "vref_1p25";

				qcom,pre-scaling = <1 1>;

			};



			die_temp {

				reg = <ADC5_DIE_TEMP>;

				label = "die_temp";

				qcom,pre-scaling = <1 1>;

			};

		};



		qcom,power-on@800 {

			compatible = "qcom,qpnp-power-on";

			reg = <0x800>;

		};



		pm8195_3_clkdiv: clock-controller@5b00 {

			compatible = "qcom,spmi-clkdiv";

			reg = <0x5b00>;

			#clock-cells = <1>;

			qcom,num-clkdivs = <2>;

			clock-output-names = "pm8195_3_div_clk1",

						"pm8195_3_div_clk2";

			clocks = <&rpmhcc RPMH_CXO_CLK>;

			clock-names = "xo";

		};



		pm8195_3_gpios: pinctrl@c000 {

			compatible = "qcom,pm8150-gpio";

			reg = <0xc000>;

			gpio-controller;

			#gpio-cells = <2>;

			interrupt-controller;

			#interrupt-cells = <2>;

		};

	};



	qcom,pm8195@9 {

		compatible ="qcom,spmi-pmic";

		reg = <9 SPMI_USID>;

		#address-cells = <1>;

		#size-cells = <1>;

	};

};



/* PMIC GPIO pin control configurations */

&pm8195_1_gpios {

	storage_sd_detect {

		storage_cd_default: storage_cd_default {

			pins = "gpio4";

			function = "normal";

			input-enable;

			bias-pull-up;

			power-source = <0>;

		};

	};



	key_vol_up {

		key_vol_up_default: key_vol_up_default {

			pins = "gpio6";

			function = "normal";

			input-enable;

			bias-pull-up;

			power-source = <1>;

		};

	};

};

qcom/sa8195-pmic.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -69,3 +69,4 @@ 
};



#include "sa8195p-regulator.dtsi"

#include "pm8195.dtsi"

qcom/sa8195p.dtsi

+30 −0
Original line number Diff line number Diff line
@@ -11,3 +11,33 @@ 
	vdd_scc_cx-supply = <&VDD_SCC_CX_LEVEL>;

	status = "ok";

};



&ufsphy_mem {

	compatible = "qcom,ufs-phy-qmp-v4";

	vdda-phy-supply = <&pm8195_3_l5>;

	vdda-pll-supply = <&pm8195_1_l9>;

	vdda-phy-max-microamp = <138000>;

	vdda-pll-max-microamp = <65100>;



	status = "ok";

};



&ufshc_mem {

	vdd-hba-supply = <&ufs_phy_gdsc>;

	vdd-hba-fixed-regulator;

	vcc-supply = <&pm8195_3_l10>;

	vcc-voltage-level = <2894000 2904000>;

	vcc-low-voltage-sup;

	vccq-supply = <&pm8195_1_l11>;

	vccq2-supply = <&pm8195_3_l7>;

	vcc-max-microamp = <750000>;

	vccq-max-microamp = <750000>;

	vccq2-max-microamp = <750000>;



	qcom,vddp-ref-clk-supply = <&pm8195_2_l5>;

	qcom,vddp-ref-clk-max-microamp = <100>;

	qcom,vccq-parent-supply = <&pm8195_1_s2>;

	qcom,vccq-parent-max-microamp = <210000>;



	status= "ok";

};

qcom/sdmshrike.dtsi

+157 −0
Original line number Diff line number Diff line
@@ -7,11 +7,14 @@ 
#include <dt-bindings/clock/qcom,scc-sm8150.h>

#include <dt-bindings/clock/qcom,videocc-sm8150.h>

#include <dt-bindings/clock/qcom,rpmh.h>

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/interconnect/qcom,icc.h>

#include <dt-bindings/interconnect/qcom,osm-l3.h>

#include <dt-bindings/interconnect/qcom,scshrike.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/soc/qcom,rpmh-rsc.h>

#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>

#include <dt-bindings/spmi/spmi.h>



/ {

	model = "Qualcomm Technologies, Inc. SDMSHRIKE";
@@ -26,6 +29,7 @@ 


	aliases {

		serial0 = &uart2;

		ufshc1 = &ufshc_mem; /* Embedded UFS slot */

	};



	cpus {
@@ -974,6 +978,159 @@ 
		#freq-domain-cells = <2>;

	};



	ufsphy_mem: ufsphy_mem@1d87000 {

		reg = <0x1d87000 0xe00>; /* PHY regs */

		reg-names = "phy_mem";

		#phy-cells = <0>;



		lanes-per-direction = <2>;



		clock-names = "ref_clk_src",

			"ref_clk",

			"ref_aux_clk";

		clocks = <&rpmhcc RPMH_CXO_CLK>,

			<&gcc GCC_UFS_MEM_CLKREF_CLK>,

			<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;



		resets = <&ufshc_mem 0>;

		status = "disabled";

	};



	ufshc_mem: ufshc@1d84000 {

		compatible = "qcom,ufshc";

		reg = <0x1d84000 0x3000>,

			  <0x1d90000 0x8000>;

		reg-names = "ufs_mem", "ufs_ice";

		interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;

		phys = <&ufsphy_mem>;

		phy-names = "ufsphy";

		#reset-cells = <1>;



		lanes-per-direction = <2>;

		dev-ref-clk-freq = <0>; /* 19.2 MHz */



		clock-names =

			"core_clk",

			"bus_aggr_clk",

			"iface_clk",

			"core_clk_unipro",

			"core_clk_ice",

			"ref_clk",

			"tx_lane0_sync_clk",

			"rx_lane0_sync_clk",

			"rx_lane1_sync_clk";

		clocks =

			<&gcc GCC_UFS_PHY_AXI_CLK>,

			<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,

			<&gcc GCC_UFS_PHY_AHB_CLK>,

			<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,

			<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,

			<&rpmhcc RPMH_CXO_CLK>,

			<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,

			<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,

			<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;

		freq-table-hz =

			<37500000 300000000>,

			<0 0>,

			<0 0>,

			<37500000 300000000>,

			<37500000 300000000>,

			<0 0>,

			<0 0>,

			<0 0>,

			<0 0>;

		interconnects =

			<&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,

			<&gem_noc MASTER_APPSS_PROC

					&config_noc SLAVE_UFS_MEM_0_CFG>;

		interconnect-names = "ufs-ddr", "cpu-ufs";



		qcom,ufs-bus-bw,name = "ufshc_mem";

		qcom,ufs-bus-bw,num-cases = <26>;

		qcom,ufs-bus-bw,num-paths = <2>;

		qcom,ufs-bus-bw,vectors-KBps =

		/*

		 * During HS G3 UFS runs at nominal voltage corner, vote

		 * higher bandwidth to push other buses in the data path

		 * to run at nominal to achieve max throughput.

		 * 4GBps pushes BIMC to run at nominal.

		 * 200MBps pushes CNOC to run at nominal.

		 * Vote for half of this bandwidth for HS G3 1-lane.

		 * For max bandwidth, vote high enough to push the buses

		 * to run in turbo voltage corner.

		 */

		<0 0>, <0 0>,          /* No vote */

		<922 0>, <1000 0>,     /* PWM G1 */

		<1844 0>, <1000 0>,    /* PWM G2 */

		<3688 0>, <1000 0>,    /* PWM G3 */

		<7376 0>, <1000 0>,    /* PWM G4 */

		<1844 0>, <1000 0>,    /* PWM G1 L2 */

		<3688 0>, <1000 0>,    /* PWM G2 L2 */

		<7376 0>, <1000 0>,    /* PWM G3 L2 */

		<14752 0>, <1000 0>,   /* PWM G4 L2 */

		<127796 0>, <1000 0>,  /* HS G1 RA */

		<255591 0>, <1000 0>,  /* HS G2 RA */

		<2097152 0>, <102400 0>,  /* HS G3 RA */

		<4194304 0>, <204800 0>,  /* HS G4 RA */

		<255591 0>, <1000 0>,  /* HS G1 RA L2 */

		<511181 0>, <1000 0>,  /* HS G2 RA L2 */

		<4194304 0>, <204800 0>, /* HS G3 RA L2 */

		<8388608 0>, <409600 0>, /* HS G4 RA L2 */

		<149422 0>, <1000 0>,  /* HS G1 RB */

		<298189 0>, <1000 0>,  /* HS G2 RB */

		<2097152 0>, <102400 0>,  /* HS G3 RB */

		<4194304 0>, <204800 0>,  /* HS G4 RB */

		<298189 0>, <1000 0>,  /* HS G1 RB L2 */

		<596378 0>, <1000 0>,  /* HS G2 RB L2 */

		/* As UFS working in HS G3 RB L2 mode, aggregated

		 * bandwidth (AB) should take care of providing

		 * optimum throughput requested. However, as tested,

		 * in order to scale up CNOC clock, instantaneous

		 * bindwidth (IB) needs to be given a proper value too.

		 */

		<4194304 0>, <204800 409600>, /* HS G3 RB L2 */

		<8388608 0>, <409600 409600>, /* HS G4 RB L2 */

		<7643136 0>, <307200 0>; /* Max. bandwidth */



		qcom,bus-vector-names = "MIN",

		"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",

		"PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",

		"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1",

		"HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2",

		"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1",

		"HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2",

		"MAX";



		reset-gpios = <&tlmm 190 GPIO_ACTIVE_LOW>;



		resets = <&gcc GCC_UFS_PHY_BCR>;

		reset-names = "rst";



		status = "disabled";

	};



	spmi_bus: qcom,spmi@c440000 {

		compatible = "qcom,spmi-pmic-arb";

		reg = <0xc440000 0x1000>,

		      <0xc600000 0x2000000>,

		      <0xe600000 0x100000>,

		      <0xe700000 0xa0000>,

		      <0xc40a000 0x700>;

		reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";

		interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "periph_irq";

		interrupt-controller;

		#interrupt-cells = <4>;

		#address-cells = <2>;

		#size-cells = <0>;

		cell-index = <0>;

		qcom,channel = <0>;

		qcom,ee = <0>;

	};



	thermal_zones: thermal-zones {

	};



	tcsr_mutex_block: syscon@1f40000 {

		compatible = "syscon";

		reg = <0x1f40000 0x20000>;