Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 48d59871 authored by Veera Vegivada's avatar Veera Vegivada
Browse files

ARM: dts: msm: add PMIC devices for SCSHRIKE 

Add top level SPMI slave devices for PM8195.
Also add some of the peripheral devices within the SPMI slave devices.

Change-Id: Ic6fc5967aef72f72398ef99057aa3fe9f84a1753
parent 5af26faa

qcom/pm8195.dtsi

0 → 100644
+307 −0
Original line number Diff line number Diff line 
#include <dt-bindings/clock/qcom,rpmh.h>

#include <dt-bindings/iio/qcom,spmi-vadc.h>

#include <dt-bindings/input/input.h>

#include <dt-bindings/input/qcom,qpnp-power-on.h>

#include <dt-bindings/interrupt-controller/irq.h>

#include <dt-bindings/spmi/spmi.h>



&spmi_bus {

	#address-cells = <2>;

	#size-cells = <0>;

	interrupt-controller;

	#interrupt-cells = <4>;



	qcom,pm8195@0 {

		compatible = "qcom,spmi-pmic";

		reg = <0 SPMI_USID>;

		#address-cells = <1>;

		#size-cells = <0>;



		pm8195_1_tz: qcom,temp-alarm@2400 {

			compatible = "qcom,spmi-temp-alarm";

			reg = <0x2400>;

			interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;

			io-channels = <&pm8195_1_vadc ADC5_DIE_TEMP>;

			io-channel-names = "thermal";

			#thermal-sensor-cells = <0>;

			qcom,temperature-threshold-set = <1>;

		};



		pm8195_1_vadc: vadc@3100 {

			compatible = "qcom,spmi-adc5";

			reg = <0x3100>;

			#address-cells = <1>;

			#size-cells = <0>;

			interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;

			interrupt-names = "eoc-int-en-set";

			#io-channel-cells = <1>;

			io-channel-ranges;



			/* Channel node */

			ref_gnd {

				reg = <ADC5_REF_GND>;

				label = "ref_gnd";

				qcom,pre-scaling = <1 1>;

			};



			vref_1p25 {

				reg = <ADC5_1P25VREF>;

				label = "vref_1p25";

				qcom,pre-scaling = <1 1>;

			};



			die_temp {

				reg = <ADC5_DIE_TEMP>;

				label = "die_temp";

				qcom,pre-scaling = <1 1>;

			};

		};



		qcom,power-on@800 {

			compatible = "qcom,qpnp-power-on";

			reg = <0x800>;

			interrupts = <0x0 0x8 0x0 IRQ_TYPE_NONE>,

				     <0x0 0x8 0x1 IRQ_TYPE_NONE>;

			interrupt-names = "kpdpwr", "resin";

			qcom,pon-dbc-delay = <15625>;

			qcom,kpdpwr-sw-debounce;

			qcom,system-reset;

			qcom,store-hard-reset-reason;



			qcom,pon_1 {

				qcom,pon-type = <PON_POWER_ON_TYPE_KPDPWR>;

				qcom,pull-up;

				linux,code = <KEY_POWER>;

			};



			qcom,pon_2 {

				qcom,pon-type = <PON_POWER_ON_TYPE_RESIN>;

				qcom,pull-up;

				linux,code = <KEY_VOLUMEDOWN>;

			};

		};



		pm8195_1_clkdiv: clock-controller@5b00 {

			compatible = "qcom,spmi-clkdiv";

			reg = <0x5b00>;

			#clock-cells = <1>;

			qcom,num-clkdivs = <2>;

			clock-output-names = "pm8195_1_div_clk1",

						"pm8195_1_div_clk2";

			clocks = <&rpmhcc RPMH_CXO_CLK>;

			clock-names = "xo";

		};



		pm8195_1_rtc: qcom,pm8195_1_rtc {

			compatible = "qcom,pm8941-rtc";

			reg = <0x6000>, <0x6100>;

			reg-names = "rtc", "alarm";

			interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;

		};



		pm8195_1_gpios: pinctrl@c000 {

			compatible = "qcom,pm8150-gpio";

			reg = <0xc000>;

			gpio-controller;

			#gpio-cells = <2>;

			interrupt-controller;

			#interrupt-cells = <2>;

		};



		pm8195_1_sdam_2: sdam@b100 {

			compatible = "qcom,spmi-sdam";

			reg = <0xb100>;

		};



	};



	qcom,pm8195@1 {

		compatible ="qcom,spmi-pmic";

		reg = <1 SPMI_USID>;

		#address-cells = <2>;

		#size-cells = <0>;

	};



	/* below definitions are for the second instance of pm8195 */

	qcom,pm8195@4 {

		compatible = "qcom,spmi-pmic";

		reg = <4 SPMI_USID>;

		#address-cells = <1>;

		#size-cells = <0>;



		pm8195_2_tz: qcom,temp-alarm@2400 {

			compatible = "qcom,spmi-temp-alarm";

			reg = <0x2400>;

			interrupts = <0x4 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;

			io-channels = <&pm8195_2_vadc ADC5_DIE_TEMP>;

			io-channel-names = "thermal";

			#thermal-sensor-cells = <0>;

			qcom,temperature-threshold-set = <1>;

		};



		pm8195_2_vadc: vadc@3100 {

			compatible = "qcom,spmi-adc5";

			reg = <0x3100>;

			#address-cells = <1>;

			#size-cells = <0>;

			interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>;

			interrupt-names = "eoc-int-en-set";

			#io-channel-cells = <1>;

			io-channel-ranges;



			/* Channel node */

			ref_gnd {

				reg = <ADC5_REF_GND>;

				label = "ref_gnd";

				qcom,pre-scaling = <1 1>;

			};



			vref_1p25 {

				reg = <ADC5_1P25VREF>;

				label = "vref_1p25";

				qcom,pre-scaling = <1 1>;

			};



			die_temp {

				reg = <ADC5_DIE_TEMP>;

				label = "die_temp";

				qcom,pre-scaling = <1 1>;

			};

		};



		qcom,power-on@800 {

			compatible = "qcom,qpnp-power-on";

			reg = <0x800>;

		};



		pm8195_2_clkdiv: clock-controller@5b00 {

			compatible = "qcom,spmi-clkdiv";

			reg = <0x5b00>;

			#clock-cells = <1>;

			qcom,num-clkdivs = <2>;

			clock-output-names = "pm8195_2_div_clk1",

						"pm8195_2_div_clk2";

			clocks = <&rpmhcc RPMH_CXO_CLK>;

			clock-names = "xo";

		};



		pm8195_2_gpios: pinctrl@c000 {

			compatible = "qcom,pm8150-gpio";

			reg = <0xc000>;

			gpio-controller;

			#gpio-cells = <2>;

			interrupt-controller;

			#interrupt-cells = <2>;

		};

	};



	qcom,pm8195@5 {

		compatible ="qcom,spmi-pmic";

		reg = <5 SPMI_USID>;

		#address-cells = <1>;

		#size-cells = <1>;

	};



	/* below definitions are for the third instance of pm8195 */

	qcom,pm8195@8 {

		compatible = "qcom,spmi-pmic";

		reg = <8 SPMI_USID>;

		#address-cells = <1>;

		#size-cells = <0>;



		pm8195_3_tz: qcom,temp-alarm@2400 {

			compatible = "qcom,spmi-temp-alarm";

			reg = <0x2400>;

			interrupts = <0x8 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;

			io-channels = <&pm8195_3_vadc ADC5_DIE_TEMP>;

			io-channel-names = "thermal";

			#thermal-sensor-cells = <0>;

			qcom,temperature-threshold-set = <1>;

		};



		pm8195_3_vadc: vadc@3100 {

			compatible = "qcom,spmi-adc5";

			reg = <0x3100>;

			#address-cells = <1>;

			#size-cells = <0>;

			interrupts = <0x8 0x31 0x0 IRQ_TYPE_EDGE_RISING>;

			interrupt-names = "eoc-int-en-set";

			#io-channel-cells = <1>;

			io-channel-ranges;



			/* Channel node */

			ref_gnd {

				reg = <ADC5_REF_GND>;

				label = "ref_gnd";

				qcom,pre-scaling = <1 1>;

			};



			vref_1p25 {

				reg = <ADC5_1P25VREF>;

				label = "vref_1p25";

				qcom,pre-scaling = <1 1>;

			};



			die_temp {

				reg = <ADC5_DIE_TEMP>;

				label = "die_temp";

				qcom,pre-scaling = <1 1>;

			};

		};



		qcom,power-on@800 {

			compatible = "qcom,qpnp-power-on";

			reg = <0x800>;

		};



		pm8195_3_clkdiv: clock-controller@5b00 {

			compatible = "qcom,spmi-clkdiv";

			reg = <0x5b00>;

			#clock-cells = <1>;

			qcom,num-clkdivs = <2>;

			clock-output-names = "pm8195_3_div_clk1",

						"pm8195_3_div_clk2";

			clocks = <&rpmhcc RPMH_CXO_CLK>;

			clock-names = "xo";

		};



		pm8195_3_gpios: pinctrl@c000 {

			compatible = "qcom,pm8150-gpio";

			reg = <0xc000>;

			gpio-controller;

			#gpio-cells = <2>;

			interrupt-controller;

			#interrupt-cells = <2>;

		};

	};



	qcom,pm8195@9 {

		compatible ="qcom,spmi-pmic";

		reg = <9 SPMI_USID>;

		#address-cells = <1>;

		#size-cells = <1>;

	};

};



/* PMIC GPIO pin control configurations */

&pm8195_1_gpios {

	storage_sd_detect {

		storage_cd_default: storage_cd_default {

			pins = "gpio4";

			function = "normal";

			input-enable;

			bias-pull-up;

			power-source = <0>;

		};

	};



	key_vol_up {

		key_vol_up_default: key_vol_up_default {

			pins = "gpio6";

			function = "normal";

			input-enable;

			bias-pull-up;

			power-source = <1>;

		};

	};

};

qcom/sa8195-pmic.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -69,3 +69,4 @@ 
};



#include "sa8195p-regulator.dtsi"

#include "pm8195.dtsi"

qcom/sdmshrike.dtsi

+24 −0
Original line number Diff line number Diff line
@@ -13,6 +13,8 @@ 
#include <dt-bindings/interconnect/qcom,scshrike.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/soc/qcom,rpmh-rsc.h>

#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>

#include <dt-bindings/spmi/spmi.h>



/ {

	model = "Qualcomm Technologies, Inc. SDMSHRIKE";
@@ -1107,6 +1109,28 @@ 
		status = "disabled";

	};



	spmi_bus: qcom,spmi@c440000 {

		compatible = "qcom,spmi-pmic-arb";

		reg = <0xc440000 0x1000>,

		      <0xc600000 0x2000000>,

		      <0xe600000 0x100000>,

		      <0xe700000 0xa0000>,

		      <0xc40a000 0x700>;

		reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";

		interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "periph_irq";

		interrupt-controller;

		#interrupt-cells = <4>;

		#address-cells = <2>;

		#size-cells = <0>;

		cell-index = <0>;

		qcom,channel = <0>;

		qcom,ee = <0>;

	};



	thermal_zones: thermal-zones {

	};



	tcsr_mutex_block: syscon@1f40000 {

		compatible = "syscon";

		reg = <0x1f40000 0x20000>;