Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit e4eabf27 authored by Joonas Lahtinen's avatar Joonas Lahtinen
Browse files

Merge tag 'gvt-next-2019-04-16' of https://github.com/intel/gvt-linux into drm-intel-next-queued 



gvt-next-2019-04-16

- Refine range of MCHBAR snapshot (Yakui)
- Refine out-of-sync page struct (Yakui)
- Remove unused vGPU sreg (Yan)
- Refind MMIO reg names (Xiaolin)
- Proper handling of sync/async flip (Colin)
- Proper handling of PIPE_CONTROL/MI_FLUSH_DW index mode (Xiaolin)
- EXCC reg mask fix (Colin)

Signed-off-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
From: Zhenyu Wang <zhenyuw@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190416084814.GH17995@zhen-hp.sh.intel.com
parents adc674ce 2bfc4975

drivers/gpu/drm/i915/gvt/cmd_parser.c

+28 −2
Original line number Diff line number Diff line
@@ -1077,6 +1077,7 @@ static int cmd_handler_pipe_control(struct parser_exec_state *s) 
	bool index_mode = false;

	unsigned int post_sync;

	int ret = 0;

	u32 hws_pga, val;



	post_sync = (cmd_val(s, 1) & PIPE_CONTROL_POST_SYNC_OP_MASK) >> 14;
@@ -1100,6 +1101,15 @@ static int cmd_handler_pipe_control(struct parser_exec_state *s) 
					index_mode = true;

				ret |= cmd_address_audit(s, gma, sizeof(u64),

						index_mode);

				if (ret)

					return ret;

				if (index_mode) {

					hws_pga = s->vgpu->hws_pga[s->ring_id];

					gma = hws_pga + gma;

					patch_value(s, cmd_ptr(s, 2), gma);

					val = cmd_val(s, 1) & (~(1 << 21));

					patch_value(s, cmd_ptr(s, 1), val);

				}

			}

		}

	}
@@ -1317,8 +1327,14 @@ static int gen8_update_plane_mmio_from_mi_display_flip( 
			      info->tile_val << 10);

	}



	vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(info->pipe))++;

	if (info->plane == PLANE_PRIMARY)

		vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(info->pipe))++;



	if (info->async_flip)

		intel_vgpu_trigger_virtual_event(vgpu, info->event);

	else

		set_bit(info->event, vgpu->irq.flip_done_event[info->pipe]);



	return 0;

}
@@ -1563,6 +1579,7 @@ static int cmd_handler_mi_flush_dw(struct parser_exec_state *s) 
	unsigned long gma;

	bool index_mode = false;

	int ret = 0;

	u32 hws_pga, val;



	/* Check post-sync and ppgtt bit */

	if (((cmd_val(s, 0) >> 14) & 0x3) && (cmd_val(s, 1) & (1 << 2))) {
@@ -1573,6 +1590,15 @@ static int cmd_handler_mi_flush_dw(struct parser_exec_state *s) 
		if (cmd_val(s, 0) & (1 << 21))

			index_mode = true;

		ret = cmd_address_audit(s, gma, sizeof(u64), index_mode);

		if (ret)

			return ret;

		if (index_mode) {

			hws_pga = s->vgpu->hws_pga[s->ring_id];

			gma = hws_pga + gma;

			patch_value(s, cmd_ptr(s, 1), gma);

			val = cmd_val(s, 0) & (~(1 << 21));

			patch_value(s, cmd_ptr(s, 0), val);

		}

	}

	/* Check notify bit */

	if ((cmd_val(s, 0) & (1 << 8)))

drivers/gpu/drm/i915/gvt/display.c

+0 −1
Original line number Diff line number Diff line
@@ -407,7 +407,6 @@ static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe) 
		if (!pipe_is_enabled(vgpu, pipe))

			continue;



		vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;

		intel_vgpu_trigger_virtual_event(vgpu, event);

	}

drivers/gpu/drm/i915/gvt/gtt.c

+7 −0
Original line number Diff line number Diff line
@@ -2489,6 +2489,7 @@ static void clean_spt_oos(struct intel_gvt *gvt) 
	list_for_each_safe(pos, n, &gtt->oos_page_free_list_head) {

		oos_page = container_of(pos, struct intel_vgpu_oos_page, list);

		list_del(&oos_page->list);

		free_page((unsigned long)oos_page->mem);

		kfree(oos_page);

	}

}
@@ -2509,6 +2510,12 @@ static int setup_spt_oos(struct intel_gvt *gvt) 
			ret = -ENOMEM;

			goto fail;

		}

		oos_page->mem = (void *)__get_free_pages(GFP_KERNEL, 0);

		if (!oos_page->mem) {

			ret = -ENOMEM;

			kfree(oos_page);

			goto fail;

		}



		INIT_LIST_HEAD(&oos_page->list);

		INIT_LIST_HEAD(&oos_page->vm_list);

drivers/gpu/drm/i915/gvt/gtt.h

+1 −1
Original line number Diff line number Diff line
@@ -221,7 +221,7 @@ struct intel_vgpu_oos_page { 
	struct list_head list;

	struct list_head vm_list;

	int id;

	unsigned char mem[I915_GTT_PAGE_SIZE];

	void *mem;

};



#define GTT_ENTRY_NUM_IN_ONE_PAGE 512

drivers/gpu/drm/i915/gvt/gvt.h

+1 −8
Original line number Diff line number Diff line
@@ -94,7 +94,6 @@ struct intel_vgpu_fence { 


struct intel_vgpu_mmio {

	void *vreg;

	void *sreg;

};



#define INTEL_GVT_MAX_BAR_NUM 4
@@ -111,11 +110,9 @@ struct intel_vgpu_cfg_space { 


#define vgpu_cfg_space(vgpu) ((vgpu)->cfg_space.virtual_cfg_space)



#define INTEL_GVT_MAX_PIPE 4



struct intel_vgpu_irq {

	bool irq_warn_once[INTEL_GVT_EVENT_MAX];

	DECLARE_BITMAP(flip_done_event[INTEL_GVT_MAX_PIPE],

	DECLARE_BITMAP(flip_done_event[I915_MAX_PIPES],

		       INTEL_GVT_EVENT_MAX);

};
@@ -449,10 +446,6 @@ void intel_vgpu_write_fence(struct intel_vgpu *vgpu, 
	(*(u64 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))

#define vgpu_vreg64(vgpu, offset) \

	(*(u64 *)(vgpu->mmio.vreg + (offset)))

#define vgpu_sreg_t(vgpu, reg) \

	(*(u32 *)(vgpu->mmio.sreg + i915_mmio_reg_offset(reg)))

#define vgpu_sreg(vgpu, offset) \

	(*(u32 *)(vgpu->mmio.sreg + (offset)))



#define for_each_active_vgpu(gvt, vgpu, id) \

	idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) \