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Commit 2bfc4975 authored by Colin Xu's avatar Colin Xu Committed by Zhenyu Wang
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drm/i915/gvt: Fix incorrect mask of mmio 0x22028 in gen8/9 mmio list 



According to GFX PRM on 01.org, bit 31:16 of mmio 0x22028 should be masks.

Fixes: 17865713 ("drm/i915/gvt: vGPU context switch")
Reviewed-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: default avatarColin Xu <colin.xu@intel.com>
Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
parent ac071578

drivers/gpu/drm/i915/gvt/mmio_context.c

+2 −2
Original line number Diff line number Diff line
@@ -68,7 +68,7 @@ static struct engine_mmio gen8_engine_mmio_list[] __cacheline_aligned = { 
	{BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */

	{BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */

	{BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */

	{BCS0, RING_EXCC(BLT_RING_BASE), 0x0, false}, /* 0x22028 */

	{BCS0, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */

	{RCS0, INVALID_MMIO_REG, 0, false } /* Terminated */

};
@@ -119,7 +119,7 @@ static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = { 
	{BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */

	{BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */

	{BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */

	{BCS0, RING_EXCC(BLT_RING_BASE), 0x0, false}, /* 0x22028 */

	{BCS0, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */



	{VCS1, RING_EXCC(GEN8_BSD2_RING_BASE), 0xffff, false}, /* 0x1c028 */