Merge tag 'zynqmp-soc-clk-for-v4.20' of https://github.com/Xilinx/linux-xlnx into next/drivers

		  - "smc" : SMC #0, following the SMCCC

		  - "hvc" : HVC #0, following the SMCCC

--------------------------------------------------------------------------

Device Tree Clock bindings for the Zynq Ultrascale+ MPSoC controlled using

Zynq MPSoC firmware interface

--------------------------------------------------------------------------

The clock controller is a h/w block of Zynq Ultrascale+ MPSoC clock

tree. It reads required input clock frequencies from the devicetree and acts

as clock provider for all clock consumers of PS clocks.

See clock_bindings.txt for more information on the generic clock bindings.

Required properties:

 - #clock-cells:	Must be 1

 - compatible:		Must contain:	"xlnx,zynqmp-clk"

 - clocks:		List of clock specifiers which are external input

			clocks to the given clock controller. Please refer

			the next section to find the input clocks for a

			given controller.

 - clock-names:		List of clock names which are exteral input clocks

			to the given clock controller. Please refer to the

			clock bindings for more details.

Input clocks for zynqmp Ultrascale+ clock controller:

The Zynq UltraScale+ MPSoC has one primary and four alternative reference clock

inputs. These required clock inputs are:

 - pss_ref_clk (PS reference clock)

 - video_clk (reference clock for video system )

 - pss_alt_ref_clk (alternative PS reference clock)

 - aux_ref_clk

 - gt_crx_ref_clk (transceiver reference clock)

The following strings are optional parameters to the 'clock-names' property in

order to provide an optional (E)MIO clock source:

 - swdt0_ext_clk

 - swdt1_ext_clk

 - gem0_emio_clk

 - gem1_emio_clk

 - gem2_emio_clk

 - gem3_emio_clk

 - mio_clk_XX		# with XX = 00..77

 - mio_clk_50_or_51	#for the mux clock to gem tsu from 50 or 51

Output clocks are registered based on clock information received

from firmware. Output clocks indexes are mentioned in

include/dt-bindings/clock/xlnx,zynqmp-clk.h.

-------

Example

-------

	zynqmp_firmware: zynqmp-firmware {

		compatible = "xlnx,zynqmp-firmware";

		method = "smc";

		zynqmp_clk: clock-controller {

			#clock-cells = <1>;

			compatible = "xlnx,zynqmp-clk";

			clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <&gt_crx_ref_clk>;

			clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";

		};

	};

};

---------------------------------------------------------------------

Xilinx Zynq MPSoC EEMI Documentation

---------------------------------------------------------------------

Xilinx Zynq MPSoC Firmware Interface

-------------------------------------

The zynqmp-firmware node describes the interface to platform firmware.

ZynqMP has an interface to communicate with secure firmware. Firmware

driver provides an interface to firmware APIs. Interface APIs can be

used by any driver to communicate with PMC(Platform Management Controller).

Embedded Energy Management Interface (EEMI)

----------------------------------------------

The embedded energy management interface is used to allow software

components running across different processing clusters on a chip or

device to communicate with a power management controller (PMC) on a

device to issue or respond to power management requests.

EEMI ops is a structure containing all eemi APIs supported by Zynq MPSoC.

The zynqmp-firmware driver maintain all EEMI APIs in zynqmp_eemi_ops

structure. Any driver who want to communicate with PMC using EEMI APIs

can call zynqmp_pm_get_eemi_ops().

Example of EEMI ops:

	/* zynqmp-firmware driver maintain all EEMI APIs */

	struct zynqmp_eemi_ops {

		int (*get_api_version)(u32 *version);

		int (*query_data)(struct zynqmp_pm_query_data qdata, u32 *out);

	};

	static const struct zynqmp_eemi_ops eemi_ops = {

		.get_api_version = zynqmp_pm_get_api_version,

		.query_data = zynqmp_pm_query_data,

	};

Example of EEMI ops usage:

	static const struct zynqmp_eemi_ops *eemi_ops;

	u32 ret_payload[PAYLOAD_ARG_CNT];

	int ret;

	eemi_ops = zynqmp_pm_get_eemi_ops();

	if (!eemi_ops)

		return -ENXIO;

	ret = eemi_ops->query_data(qdata, ret_payload);

IOCTL

------

IOCTL API is for device control and configuration. It is not a system

IOCTL but it is an EEMI API. This API can be used by master to control

any device specific configuration. IOCTL definitions can be platform

specific. This API also manage shared device configuration.

The following IOCTL IDs are valid for device control:

- IOCTL_SET_PLL_FRAC_MODE	8

- IOCTL_GET_PLL_FRAC_MODE	9

- IOCTL_SET_PLL_FRAC_DATA	10

- IOCTL_GET_PLL_FRAC_DATA	11

Refer EEMI API guide [0] for IOCTL specific parameters and other EEMI APIs.

References

----------

[0] Embedded Energy Management Interface (EEMI) API guide:

    https://www.xilinx.com/support/documentation/user_guides/ug1200-eemi-api.pdf

source "drivers/clk/tegra/Kconfig"

source "drivers/clk/ti/Kconfig"

source "drivers/clk/uniphier/Kconfig"

source "drivers/clk/zynqmp/Kconfig"

endmenu

endif

obj-$(CONFIG_ARCH_ZX)			+= zte/

obj-$(CONFIG_ARCH_ZYNQ)			+= zynq/

obj-$(CONFIG_COMMON_CLK_ZYNQMP)         += zynqmp/

# SPDX-License-Identifier: GPL-2.0

config COMMON_CLK_ZYNQMP

	bool "Support for Xilinx ZynqMP Ultrascale+ clock controllers"

	depends on ARCH_ZYNQMP || COMPILE_TEST

	depends on ZYNQMP_FIRMWARE

	help

	  Support for the Zynqmp Ultrascale clock controller.

	  It has a dependency on the PMU firmware.

	  Say Y if you want to include clock support.