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Commit 3fde0e16 authored by Jolly Shah's avatar Jolly Shah Committed by Michal Simek
Browse files

drivers: clk: Add ZynqMP clock driver 



This patch adds CCF compliant clock driver for ZynqMP.
Clock driver queries supported clock information from
firmware and regiters pll and output clocks with CCF.

Signed-off-by: default avatarRajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: default avatarTejas Patel <tejasp@xilinx.com>
Signed-off-by: default avatarShubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Signed-off-by: default avatarJolly Shah <jolly.shah@xilinx.com>
Acked-by: default avatarOlof Johansson <olof@lixom.net>
Reviewed-by: default avatarStephen Boyd <sboyd@kernel.org>
Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
parent 26372d09

drivers/clk/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -299,5 +299,6 @@ source "drivers/clk/sunxi-ng/Kconfig" 
source "drivers/clk/tegra/Kconfig"

source "drivers/clk/ti/Kconfig"

source "drivers/clk/uniphier/Kconfig"

source "drivers/clk/zynqmp/Kconfig"



endmenu

drivers/clk/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -108,3 +108,4 @@ obj-$(CONFIG_X86) += x86/ 
endif

obj-$(CONFIG_ARCH_ZX)			+= zte/

obj-$(CONFIG_ARCH_ZYNQ)			+= zynq/

obj-$(CONFIG_COMMON_CLK_ZYNQMP)         += zynqmp/

drivers/clk/zynqmp/Kconfig

0 → 100644
+10 −0
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# SPDX-License-Identifier: GPL-2.0



config COMMON_CLK_ZYNQMP

	bool "Support for Xilinx ZynqMP Ultrascale+ clock controllers"

	depends on ARCH_ZYNQMP || COMPILE_TEST

	depends on ZYNQMP_FIRMWARE

	help

	  Support for the Zynqmp Ultrascale clock controller.

	  It has a dependency on the PMU firmware.

	  Say Y if you want to include clock support.

drivers/clk/zynqmp/Makefile

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# SPDX-License-Identifier: GPL-2.0

# Zynq Ultrascale+ MPSoC clock specific Makefile



obj-$(CONFIG_ARCH_ZYNQMP)	+= pll.o clk-gate-zynqmp.o divider.o clk-mux-zynqmp.o clkc.o

drivers/clk/zynqmp/clk-gate-zynqmp.c

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// SPDX-License-Identifier: GPL-2.0

/*

 * Zynq UltraScale+ MPSoC clock controller

 *

 *  Copyright (C) 2016-2018 Xilinx

 *

 * Gated clock implementation

 */



#include <linux/clk-provider.h>

#include <linux/slab.h>

#include "clk-zynqmp.h"



/**

 * struct clk_gate - gating clock

 * @hw:		handle between common and hardware-specific interfaces

 * @flags:	hardware-specific flags

 * @clk_id:	Id of clock

 */

struct zynqmp_clk_gate {

	struct clk_hw hw;

	u8 flags;

	u32 clk_id;

};



#define to_zynqmp_clk_gate(_hw) container_of(_hw, struct zynqmp_clk_gate, hw)



/**

 * zynqmp_clk_gate_enable() - Enable clock

 * @hw:		handle between common and hardware-specific interfaces

 *

 * Return: 0 on success else error code

 */

static int zynqmp_clk_gate_enable(struct clk_hw *hw)

{

	struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(hw);

	const char *clk_name = clk_hw_get_name(hw);

	u32 clk_id = gate->clk_id;

	int ret;

	const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();



	ret = eemi_ops->clock_enable(clk_id);



	if (ret)

		pr_warn_once("%s() clock enabled failed for %s, ret = %d\n",

			     __func__, clk_name, ret);



	return ret;

}



/*

 * zynqmp_clk_gate_disable() - Disable clock

 * @hw:		handle between common and hardware-specific interfaces

 */

static void zynqmp_clk_gate_disable(struct clk_hw *hw)

{

	struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(hw);

	const char *clk_name = clk_hw_get_name(hw);

	u32 clk_id = gate->clk_id;

	int ret;

	const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();



	ret = eemi_ops->clock_disable(clk_id);



	if (ret)

		pr_warn_once("%s() clock disable failed for %s, ret = %d\n",

			     __func__, clk_name, ret);

}



/**

 * zynqmp_clk_gate_is_enable() - Check clock state

 * @hw:		handle between common and hardware-specific interfaces

 *

 * Return: 1 if enabled, 0 if disabled else error code

 */

static int zynqmp_clk_gate_is_enabled(struct clk_hw *hw)

{

	struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(hw);

	const char *clk_name = clk_hw_get_name(hw);

	u32 clk_id = gate->clk_id;

	int state, ret;

	const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();



	ret = eemi_ops->clock_getstate(clk_id, &state);

	if (ret) {

		pr_warn_once("%s() clock get state failed for %s, ret = %d\n",

			     __func__, clk_name, ret);

		return -EIO;

	}



	return state ? 1 : 0;

}



static const struct clk_ops zynqmp_clk_gate_ops = {

	.enable = zynqmp_clk_gate_enable,

	.disable = zynqmp_clk_gate_disable,

	.is_enabled = zynqmp_clk_gate_is_enabled,

};



/**

 * zynqmp_clk_register_gate() - Register a gate clock with the clock framework

 * @name:		Name of this clock

 * @clk_id:		Id of this clock

 * @parents:		Name of this clock's parents

 * @num_parents:	Number of parents

 * @nodes:		Clock topology node

 *

 * Return: clock hardware of the registered clock gate

 */

struct clk_hw *zynqmp_clk_register_gate(const char *name, u32 clk_id,

					const char * const *parents,

					u8 num_parents,

					const struct clock_topology *nodes)

{

	struct zynqmp_clk_gate *gate;

	struct clk_hw *hw;

	int ret;

	struct clk_init_data init;



	/* allocate the gate */

	gate = kzalloc(sizeof(*gate), GFP_KERNEL);

	if (!gate)

		return ERR_PTR(-ENOMEM);



	init.name = name;

	init.ops = &zynqmp_clk_gate_ops;

	init.flags = nodes->flag;

	init.parent_names = parents;

	init.num_parents = 1;



	/* struct clk_gate assignments */

	gate->flags = nodes->type_flag;

	gate->hw.init = &init;

	gate->clk_id = clk_id;



	hw = &gate->hw;

	ret = clk_hw_register(NULL, hw);

	if (ret) {

		kfree(gate);

		hw = ERR_PTR(ret);

	}



	return hw;

}