disp: msm: dsi: skip pll clock registration for trusted vm

Trusted VM will be granted access to MDSS HW dynamically on
usecase boundary. As a result, all the attempts to access
HW before the assignment, including the probe time access
will result in Stage 2 faults. This change skips the
PLL clock registration during probe as the clocks will not
be controlled by the VM.

Change-Id: I326f4a775796cd95dcf398449b08f2682e4aca43
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>