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Commit e26612aa authored by Dhinakaran Pandiyan's avatar Dhinakaran Pandiyan Committed by Jani Nikula
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drm/dp: Bit definition for D3 power state that keeps AUX fully powered 



DPCD 600h - SET_POWER & SET_DP_PWR_VOLTAGE defines power state

101 = Set Main-Link for local Sink device and all downstream Sink
devices to D3 (power-down mode), keep AUX block fully powered, ready to
reply within a Response Timeout period of 300us.

This state is useful in a MST dock + MST monitor configuration that
doesn't wake up from D3 state.

v2: Use spaces instead of tabs (Jani)

Reviewed-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarDhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1502475008-2035-1-git-send-email-dhinakaran.pandiyan@intel.com
parent b7fa1bdb

include/drm/drm_dp_helper.h

+1 −0
Original line number Diff line number Diff line
@@ -618,6 +618,7 @@ 
# define DP_SET_POWER_D0                    0x1

# define DP_SET_POWER_D3                    0x2

# define DP_SET_POWER_MASK                  0x3

# define DP_SET_POWER_D3_AUX_ON             0x5



#define DP_EDP_DPCD_REV			    0x700    /* eDP 1.2 */

# define DP_EDP_11			    0x00