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Commit dfb19ed2 authored by Deepak M's avatar Deepak M Committed by Jani Nikula
Browse files

drm/i915: Extend gpio read/write to other cores 



Make the gpio read/write functions more generic iosf sideband read/write
functions, taking the iosf port as argument.

v2: rebase
v3: rebase
v4 by Jani: address Ville's review
v5 by Jani: drop the PCI_DEVFN change (Ville)

Signed-off-by: default avatarDeepak M <m.deepak@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1454604915-17142-1-git-send-email-jani.nikula@intel.com
parent 10182e77

drivers/gpu/drm/i915/i915_drv.h

+2 −2
Original line number Diff line number Diff line
@@ -3471,8 +3471,8 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val 
u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);

void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);

u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);

u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);

void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);

u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);

void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);

u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);

void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);

u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);

drivers/gpu/drm/i915/i915_reg.h

+2 −0
Original line number Diff line number Diff line
@@ -618,6 +618,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) 
#define   IOSF_PORT_CCK				0x14

#define   IOSF_PORT_DPIO_2			0x1a

#define   IOSF_PORT_FLISDSI			0x1b

#define   IOSF_PORT_GPIO_SC			0x48

#define   IOSF_PORT_GPIO_SUS			0xa8

#define   IOSF_PORT_CCU				0xa9

#define VLV_IOSF_DATA				_MMIO(VLV_DISPLAY_BASE + 0x2104)

#define VLV_IOSF_ADDR				_MMIO(VLV_DISPLAY_BASE + 0x2108)

drivers/gpu/drm/i915/intel_dsi_panel_vbt.c

+3 −2
Original line number Diff line number Diff line
@@ -221,14 +221,15 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) 
	if (!gtable[gpio].init) {

		/* program the function */

		/* FIXME: remove constant below */

		vlv_gpio_nc_write(dev_priv, function, 0x2000CC00);

		vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, function,

				  0x2000CC00);

		gtable[gpio].init = 1;

	}



	val = 0x4 | action;



	/* pull up/down */

	vlv_gpio_nc_write(dev_priv, pad, val);

	vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, pad, val);

	mutex_unlock(&dev_priv->sb_lock);



out:

drivers/gpu/drm/i915/intel_sideband.c

+5 −4
Original line number Diff line number Diff line
@@ -129,17 +129,18 @@ u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr) 
	return val;

}



u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg)

u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg)

{

	u32 val = 0;

	vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPIO_NC,

	vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), port,

			SB_CRRDDA_NP, reg, &val);

	return val;

}



void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)

void vlv_iosf_sb_write(struct drm_i915_private *dev_priv,

		       u8 port, u32 reg, u32 val)

{

	vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPIO_NC,

	vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), port,

			SB_CRWRDA_NP, reg, &val);

}