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Commit dda288d7 authored by Will Deacon's avatar Will Deacon Committed by Catalin Marinas
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arm64: cache: Identify VPIPT I-caches 



Add support for detecting VPIPT I-caches, as introduced by ARMv8.2.

Acked-by: default avatarMark Rutland <mark.rutland@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 02f7760e

arch/arm64/include/asm/cache.h

+7 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ 


#define CTR_L1IP(ctr)		(((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)



#define ICACHE_POLICY_VPIPT	0

#define ICACHE_POLICY_VIPT	2

#define ICACHE_POLICY_PIPT	3
@@ -45,6 +46,7 @@ 
#include <linux/bitops.h>



#define ICACHEF_ALIASING	0

#define ICACHEF_VPIPT		1

extern unsigned long __icache_flags;



/*
@@ -56,6 +58,11 @@ static inline int icache_is_aliasing(void) 
	return test_bit(ICACHEF_ALIASING, &__icache_flags);

}



static inline int icache_is_vpipt(void)

{

	return test_bit(ICACHEF_VPIPT, &__icache_flags);

}



static inline u32 cache_type_cwg(void)

{

	return (read_cpuid_cachetype() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;

arch/arm64/kernel/cpuinfo.c

+4 −0
Original line number Diff line number Diff line
@@ -46,6 +46,7 @@ static char *icache_policy_str[] = { 
	[0 ... ICACHE_POLICY_PIPT]	= "RESERVED/UNKNOWN",

	[ICACHE_POLICY_VIPT]		= "VIPT",

	[ICACHE_POLICY_PIPT]		= "PIPT",

	[ICACHE_POLICY_VPIPT]		= "VPIPT",

};



unsigned long __icache_flags;
@@ -291,6 +292,9 @@ static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info) 
	switch (l1ip) {

	case ICACHE_POLICY_PIPT:

		break;

	case ICACHE_POLICY_VPIPT:

		set_bit(ICACHEF_VPIPT, &__icache_flags);

		break;

	default:

		/* Fallthrough */

	case ICACHE_POLICY_VIPT: