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Commit 02f7760e authored by Will Deacon's avatar Will Deacon Committed by Catalin Marinas
Browse files

arm64: cache: Merge cachetype.h into cache.h 



cachetype.h and cache.h are small and both obviously related to caches.
Merge them together to reduce clutter.

Acked-by: default avatarMark Rutland <mark.rutland@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 155433cb

arch/arm64/include/asm/cache.h

+30 −1
Original line number Diff line number Diff line
@@ -16,7 +16,17 @@ 
#ifndef __ASM_CACHE_H

#define __ASM_CACHE_H



#include <asm/cachetype.h>

#include <asm/cputype.h>



#define CTR_L1IP_SHIFT		14

#define CTR_L1IP_MASK		3

#define CTR_CWG_SHIFT		24

#define CTR_CWG_MASK		15



#define CTR_L1IP(ctr)		(((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)



#define ICACHE_POLICY_VIPT	2

#define ICACHE_POLICY_PIPT	3



#define L1_CACHE_SHIFT		7

#define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)
@@ -32,6 +42,25 @@ 


#ifndef __ASSEMBLY__



#include <linux/bitops.h>



#define ICACHEF_ALIASING	0

extern unsigned long __icache_flags;



/*

 * Whilst the D-side always behaves as PIPT on AArch64, aliasing is

 * permitted in the I-cache.

 */

static inline int icache_is_aliasing(void)

{

	return test_bit(ICACHEF_ALIASING, &__icache_flags);

}



static inline u32 cache_type_cwg(void)

{

	return (read_cpuid_cachetype() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;

}



#define __read_mostly __attribute__((__section__(".data..read_mostly")))



static inline int cache_line_size(void)

arch/arm64/include/asm/cachetype.h

deleted100644 → 0
+0 −55
Original line number Diff line number Diff line 
/*

 * Copyright (C) 2012 ARM Ltd.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program.  If not, see <http://www.gnu.org/licenses/>.

 */

#ifndef __ASM_CACHETYPE_H

#define __ASM_CACHETYPE_H



#include <asm/cputype.h>



#define CTR_L1IP_SHIFT		14

#define CTR_L1IP_MASK		3

#define CTR_CWG_SHIFT		24

#define CTR_CWG_MASK		15



#define ICACHE_POLICY_VIPT	2

#define ICACHE_POLICY_PIPT	3



#ifndef __ASSEMBLY__



#include <linux/bitops.h>



#define CTR_L1IP(ctr)	(((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)



#define ICACHEF_ALIASING	0



extern unsigned long __icache_flags;



/*

 * Whilst the D-side always behaves as PIPT on AArch64, aliasing is

 * permitted in the I-cache.

 */

static inline int icache_is_aliasing(void)

{

	return test_bit(ICACHEF_ALIASING, &__icache_flags);

}



static inline u32 cache_type_cwg(void)

{

	return (read_cpuid_cachetype() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;

}



#endif	/* __ASSEMBLY__ */



#endif	/* __ASM_CACHETYPE_H */

arch/arm64/include/asm/kvm_mmu.h

+1 −1
Original line number Diff line number Diff line
@@ -108,7 +108,7 @@ alternative_else_nop_endif 
#else



#include <asm/pgalloc.h>

#include <asm/cachetype.h>

#include <asm/cache.h>

#include <asm/cacheflush.h>

#include <asm/mmu_context.h>

#include <asm/pgtable.h>

arch/arm64/kernel/cpuinfo.c

+1 −1
Original line number Diff line number Diff line
@@ -15,7 +15,7 @@ 
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.

 */

#include <asm/arch_timer.h>

#include <asm/cachetype.h>

#include <asm/cache.h>

#include <asm/cpu.h>

#include <asm/cputype.h>

#include <asm/cpufeature.h>

arch/arm64/mm/flush.c

+1 −1
Original line number Diff line number Diff line
@@ -22,7 +22,7 @@ 
#include <linux/pagemap.h>



#include <asm/cacheflush.h>

#include <asm/cachetype.h>

#include <asm/cache.h>

#include <asm/tlbflush.h>



void sync_icache_aliases(void *kaddr, unsigned long len)