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Commit dc7066c5 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'v4.8-rockchip-clk-fixes1' of... 

Merge tag 'v4.8-rockchip-clk-fixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-fixes

Some fixes for rk3399 register errors that revealed themself
during actual use.

* tag 'v4.8-rockchip-clk-fixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: mark aclk_emmc_noc as a critical clock on rk3399
  clk: rockchip: fix incorrect GATE bits for {c, g}pll_aclk_perihp_src on rk3399
  clk: rockchip: fix incorrect aclk_emmc source gate bits on rk3399
  clk: rockchip: fix rk3399 aclk_vio gate bit
parents af7c388a a45f9d41

drivers/clk/rockchip/clk-rk3399.c

+6 −5
Original line number Diff line number Diff line
@@ -833,9 +833,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { 


	/* perihp */

	GATE(0, "cpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,

			RK3399_CLKGATE_CON(5), 0, GFLAGS),

	GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,

			RK3399_CLKGATE_CON(5), 1, GFLAGS),

	GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,

			RK3399_CLKGATE_CON(5), 0, GFLAGS),

	COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p, CLK_IGNORE_UNUSED,

			RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5, DFLAGS,

			RK3399_CLKGATE_CON(5), 2, GFLAGS),
@@ -923,9 +923,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { 
			RK3399_CLKGATE_CON(6), 14, GFLAGS),



	GATE(0, "cpll_aclk_emmc_src", "cpll", CLK_IGNORE_UNUSED,

			RK3399_CLKGATE_CON(6), 12, GFLAGS),

	GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED,

			RK3399_CLKGATE_CON(6), 13, GFLAGS),

	GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED,

			RK3399_CLKGATE_CON(6), 12, GFLAGS),

	COMPOSITE_NOGATE(ACLK_EMMC, "aclk_emmc", mux_aclk_emmc_p, CLK_IGNORE_UNUSED,

			RK3399_CLKSEL_CON(21), 7, 1, MFLAGS, 0, 5, DFLAGS),

	GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", CLK_IGNORE_UNUSED,
@@ -1071,7 +1071,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { 
	/* vio */

	COMPOSITE(ACLK_VIO, "aclk_vio", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED,

			RK3399_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,

			RK3399_CLKGATE_CON(11), 10, GFLAGS),

			RK3399_CLKGATE_CON(11), 0, GFLAGS),

	COMPOSITE_NOMUX(PCLK_VIO, "pclk_vio", "aclk_vio", 0,

			RK3399_CLKSEL_CON(43), 0, 5, DFLAGS,

			RK3399_CLKGATE_CON(11), 1, GFLAGS),
@@ -1484,6 +1484,7 @@ static const char *const rk3399_cru_critical_clocks[] __initconst = { 
	"hclk_perilp1",

	"hclk_perilp1_noc",

	"aclk_dmac0_perilp",

	"aclk_emmc_noc",

	"gpll_hclk_perilp1_src",

	"gpll_aclk_perilp0_src",

	"gpll_aclk_perihp_src",