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Commit af7c388a authored by Vince Hsu's avatar Vince Hsu Committed by Stephen Boyd
Browse files

clk: tegra: remove TEGRA_PLL_USE_LOCK for PLLD/PLLD2 



Tegra114 has a HW bug that the PLLD/PLLD2 lock bit cannot be asserted when
the DIS power domain is during up-powergating process but the clamp to this
domain is not removed yet. That causes a timeout and aborts the power
sequence, although the PLLD/PLLD2 has already locked. To remove the false
alarm, we don't use the lock for PLLD/PLLD2. Just wait 1ms and treat the
clocks as locked.

Signed-off-by: default avatarVince Hsu <vinceh@nvidia.com>
Tested-by: default avatarJonathan Hunter <jonathanh@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent e0cb1b84

drivers/clk/tegra/clk-tegra114.c

+2 −2
Original line number Diff line number Diff line
@@ -428,7 +428,7 @@ static struct tegra_clk_pll_params pll_d_params = { 
	.div_nmp = &pllp_nmp,

	.freq_table = pll_d_freq_table,

	.flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |

		 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,

		 TEGRA_PLL_HAS_LOCK_ENABLE,

};



static struct tegra_clk_pll_params pll_d2_params = {
@@ -446,7 +446,7 @@ static struct tegra_clk_pll_params pll_d2_params = { 
	.div_nmp = &pllp_nmp,

	.freq_table = pll_d_freq_table,

	.flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |

		 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,

		 TEGRA_PLL_HAS_LOCK_ENABLE,

};



static const struct pdiv_map pllu_p[] = {