Loading asoc/lahaina-port-config.h +19 −2 Original line number Diff line number Diff line Loading @@ -53,8 +53,8 @@ static struct port_params tx_frame_params_default[SWR_MSTR_PORT_LEN] = { /* TX UC1: TX1: 1ch, TX2: 2chs, TX3: 1ch(MBHC) */ static struct port_params tx_frame_params_shima[SWR_MSTR_PORT_LEN] = { {3, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX1 */ {3, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 1, 0x00, 0x00}, /* TX2 */ {3, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 1, 0x00, 0x00}, /* TX1 */ {3, 2, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX2 */ {7, 2, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX3 */ }; Loading @@ -71,6 +71,21 @@ static struct port_params tx_frame_params_0p6MHz[SWR_MSTR_PORT_LEN] = { {1, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX2 */ {1, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX3 */ }; /* 4.8 MHz clock */ static struct port_params tx_frame_params_shima_4p8MHz[SWR_MSTR_PORT_LEN] = { {3, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 1, 0x00, 0x00}, /* TX1 */ {3, 2, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX2 */ {7, 2, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX3 */ }; /* 0.6 MHz clock */ static struct port_params tx_frame_params_shima_0p6MHz[SWR_MSTR_PORT_LEN] = { {1, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX1 */ {1, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX2 */ {1, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX3 */ }; static struct swr_mstr_port_map sm_port_map[] = { {TX_MACRO, SWR_UC0, tx_frame_params_default}, {TX_MACRO, SWR_UC1, tx_frame_params_4p8MHz}, Loading @@ -82,6 +97,8 @@ static struct swr_mstr_port_map sm_port_map[] = { static struct swr_mstr_port_map sm_port_map_shima[] = { {TX_MACRO, SWR_UC0, tx_frame_params_shima}, {TX_MACRO, SWR_UC1, tx_frame_params_shima_4p8MHz}, {TX_MACRO, SWR_UC2, tx_frame_params_shima_0p6MHz}, {RX_MACRO, SWR_UC0, rx_frame_params_default}, {RX_MACRO, SWR_UC1, rx_frame_params_dsd}, {WSA_MACRO, SWR_UC0, wsa_frame_params_default}, Loading asoc/lahaina.c +1 −1 Original line number Diff line number Diff line Loading @@ -7733,7 +7733,7 @@ static int msm_rx_tx_codec_init(struct snd_soc_pcm_runtime *rtd) card = rtd->card->snd_card; if (strnstr(rtd->card->name, "shima", 5) != NULL) if (strnstr(rtd->card->name, "shima", strlen(rtd->card->name)) != NULL) bolero_set_port_map(component, ARRAY_SIZE(sm_port_map_shima), sm_port_map_shima); else Loading Loading
asoc/lahaina-port-config.h +19 −2 Original line number Diff line number Diff line Loading @@ -53,8 +53,8 @@ static struct port_params tx_frame_params_default[SWR_MSTR_PORT_LEN] = { /* TX UC1: TX1: 1ch, TX2: 2chs, TX3: 1ch(MBHC) */ static struct port_params tx_frame_params_shima[SWR_MSTR_PORT_LEN] = { {3, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX1 */ {3, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 1, 0x00, 0x00}, /* TX2 */ {3, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 1, 0x00, 0x00}, /* TX1 */ {3, 2, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX2 */ {7, 2, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX3 */ }; Loading @@ -71,6 +71,21 @@ static struct port_params tx_frame_params_0p6MHz[SWR_MSTR_PORT_LEN] = { {1, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX2 */ {1, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX3 */ }; /* 4.8 MHz clock */ static struct port_params tx_frame_params_shima_4p8MHz[SWR_MSTR_PORT_LEN] = { {3, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 1, 0x00, 0x00}, /* TX1 */ {3, 2, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX2 */ {7, 2, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX3 */ }; /* 0.6 MHz clock */ static struct port_params tx_frame_params_shima_0p6MHz[SWR_MSTR_PORT_LEN] = { {1, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX1 */ {1, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX2 */ {1, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX3 */ }; static struct swr_mstr_port_map sm_port_map[] = { {TX_MACRO, SWR_UC0, tx_frame_params_default}, {TX_MACRO, SWR_UC1, tx_frame_params_4p8MHz}, Loading @@ -82,6 +97,8 @@ static struct swr_mstr_port_map sm_port_map[] = { static struct swr_mstr_port_map sm_port_map_shima[] = { {TX_MACRO, SWR_UC0, tx_frame_params_shima}, {TX_MACRO, SWR_UC1, tx_frame_params_shima_4p8MHz}, {TX_MACRO, SWR_UC2, tx_frame_params_shima_0p6MHz}, {RX_MACRO, SWR_UC0, rx_frame_params_default}, {RX_MACRO, SWR_UC1, rx_frame_params_dsd}, {WSA_MACRO, SWR_UC0, wsa_frame_params_default}, Loading
asoc/lahaina.c +1 −1 Original line number Diff line number Diff line Loading @@ -7733,7 +7733,7 @@ static int msm_rx_tx_codec_init(struct snd_soc_pcm_runtime *rtd) card = rtd->card->snd_card; if (strnstr(rtd->card->name, "shima", 5) != NULL) if (strnstr(rtd->card->name, "shima", strlen(rtd->card->name)) != NULL) bolero_set_port_map(component, ARRAY_SIZE(sm_port_map_shima), sm_port_map_shima); else Loading