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Commit 8c5b6cac authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "soc: swr-slave: update swr config for SWR DMIC"

parents 60477618 5dfbf073

asoc/lahaina-port-config.h

+1 −1
Original line number Diff line number Diff line
@@ -60,7 +60,7 @@ static struct port_params tx_frame_params_shima[SWR_MSTR_PORT_LEN] = { 


/* 4.8 MHz clock */

static struct port_params tx_frame_params_4p8MHz[SWR_MSTR_PORT_LEN] = {

	{3,  1,  0,  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX1 */

	{7,  1,  0,  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX1 */

	{3,  0,  0,  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 1, 0x00, 0x00}, /* TX2 */

	{3,  2,  0,  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX3 */

};

soc/swr-slave-port-config.h

+5 −5
Original line number Diff line number Diff line
@@ -71,29 +71,29 @@ static struct port_params tx_top_mic_9p6MHz[SWR_MSTR_PORT_LEN] = { 
	{7,  5,  0,  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX2 */

};



/* 3 Channel configuration */

/* 4 Channel configuration */

/* SWR DMIC0 */

static struct port_params tx_bottom_mic_4p8MHz[SWR_MSTR_PORT_LEN] = {

	{3,  2,  0,  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX1 */

	{3,  3,  0,  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX2 */

	{7,  5,  0,  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX2 */

};



/* SWR DMIC1 */

static struct port_params tx_receiver_mic_4p8MHz[SWR_MSTR_PORT_LEN] = {

	{3,  3,  0,  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX1 */

	{3,  1,  0,  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX2 */

	{7,  6,  0,  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX2 */

};



/* SWR DMIC2 */

static struct port_params tx_back_mic_4p8MHz[SWR_MSTR_PORT_LEN] = {

	{3,  3,  0,  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX1 */

	{3,  1,  0,  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX2 */

	{7,  7,  0,  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX2 */

};



/* SWR DMIC3 */

static struct port_params tx_top_mic_4p8MHz[SWR_MSTR_PORT_LEN] = {

	{3,  1,  0,  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX1 */

	{3,  2,  0,  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX2 */

	{7,  4,  0,  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX2 */

};



/* 1 Channel configuration */