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Commit d3e1cfaf authored by Linux Build Service Account's avatar Linux Build Service Account
Browse files

Merge 83779934 on remote branch 

Change-Id: If47a87f328ae7166eb61f6302b27ed6ecfa77f4e
parents 2652b828 83779934

msm/sde/sde_crtc.c

+6 −8
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.

 * Copyright (c) 2014-2021 The Linux Foundation. All rights reserved.

 * Copyright (C) 2013 Red Hat

 * Author: Rob Clark <robdclark@gmail.com>
@@ -3324,11 +3325,6 @@ static void sde_crtc_atomic_begin(struct drm_crtc *crtc, 


	if (crtc->state->mode_changed || sde_kms->perf.catalog->uidle_cfg.dirty)

		sde_core_perf_crtc_update_uidle(crtc, true);

	else if (!test_bit(SDE_CRTC_DIRTY_UIDLE, &sde_crtc->revalidate_mask) &&

			!sde_kms->perf.uidle_enabled)

		sde_core_uidle_setup_ctl(crtc, false);



	test_and_clear_bit(SDE_CRTC_DIRTY_UIDLE, &sde_crtc->revalidate_mask);



	/*

	 * Since CP properties use AXI buffer to program the
@@ -3482,6 +3478,7 @@ static void sde_crtc_destroy_state(struct drm_crtc *crtc, 
	struct sde_crtc_state *cstate;

	struct drm_encoder *enc;

	struct sde_kms *sde_kms;

	u32 encoder_mask;



	if (!crtc || !state) {

		SDE_ERROR("invalid argument(s)\n");
@@ -3497,9 +3494,11 @@ static void sde_crtc_destroy_state(struct drm_crtc *crtc, 
		return;

	}



	SDE_DEBUG("crtc%d\n", crtc->base.id);

	encoder_mask = state->encoder_mask ? state->encoder_mask :

				crtc->state->encoder_mask;

	SDE_DEBUG("crtc%d\n, encoder_mask=%d", crtc->base.id, encoder_mask);



	drm_for_each_encoder_mask(enc, crtc->dev, state->encoder_mask)

	drm_for_each_encoder_mask(enc, crtc->dev, encoder_mask)

		sde_rm_release(&sde_kms->rm, enc, true);



	__drm_atomic_helper_crtc_destroy_state(state);
@@ -3999,7 +3998,6 @@ void sde_crtc_reset_sw_state(struct drm_crtc *crtc) 


	/* mark other properties which need to be dirty for next update */

	set_bit(SDE_CRTC_DIRTY_DIM_LAYERS, &sde_crtc->revalidate_mask);

	set_bit(SDE_CRTC_DIRTY_UIDLE, &sde_crtc->revalidate_mask);

	if (cstate->num_ds_enabled)

		set_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty);

}

msm/sde/sde_crtc.h

+1 −1
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.

 * Copyright (c) 2015-2021 The Linux Foundation. All rights reserved.

 * Copyright (C) 2013 Red Hat

 * Author: Rob Clark <robdclark@gmail.com>
@@ -399,7 +400,6 @@ struct sde_crtc { 
enum sde_crtc_dirty_flags {

	SDE_CRTC_DIRTY_DEST_SCALER,

	SDE_CRTC_DIRTY_DIM_LAYERS,

	SDE_CRTC_DIRTY_UIDLE,

	SDE_CRTC_DIRTY_MAX,

};

msm/sde/sde_encoder.c

+20 −27
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.

 * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved.

 * Copyright (C) 2013 Red Hat

 * Author: Rob Clark <robdclark@gmail.com>
@@ -1376,20 +1377,9 @@ static int _sde_encoder_update_rsc_client( 
	    (rsc_config->prefill_lines != mode_info->prefill_lines) ||

	    (rsc_config->jitter_numer != mode_info->jitter_numer) ||

	    (rsc_config->jitter_denom != mode_info->jitter_denom)) {



		rsc_config->fps = mode_info->frame_rate;

		rsc_config->vtotal = mode_info->vtotal;

		/*

		 * for video mode, prefill lines should not go beyond vertical

		 * front porch for RSCC configuration. This will ensure bw

		 * downvotes are not sent within the active region. Additional

		 * -1 is to give one line time for rscc mode min_threshold.

		 */

		if (is_vid_mode && (mode_info->prefill_lines >= v_front_porch))

			rsc_config->prefill_lines = v_front_porch - 1;

		else

		rsc_config->prefill_lines = mode_info->prefill_lines;



		rsc_config->jitter_numer = mode_info->jitter_numer;

		rsc_config->jitter_denom = mode_info->jitter_denom;

		sde_enc->rsc_state_init = false;
@@ -1841,9 +1831,6 @@ static int _sde_encoder_rc_pre_modeset(struct drm_encoder *drm_enc, 
{

	int ret = 0;



	/* cancel delayed off work, if any */

	_sde_encoder_rc_cancel_delayed(sde_enc, sw_event);



	mutex_lock(&sde_enc->rc_lock);



	if (sde_enc->rc_state == SDE_ENC_RC_STATE_OFF) {
@@ -1873,19 +1860,18 @@ static int _sde_encoder_rc_pre_modeset(struct drm_encoder *drm_enc, 
		sde_enc->rc_state = SDE_ENC_RC_STATE_ON;

	}



	if (sde_encoder_has_dsc_hw_rev_2(sde_enc))

		goto skip_wait;



	ret = sde_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE);

	if (ret && ret != -EWOULDBLOCK) {

		SDE_ERROR_ENC(sde_enc,

				"wait for commit done returned %d\n",

				ret);

		SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,

				ret, SDE_EVTLOG_ERROR);

		SDE_ERROR_ENC(sde_enc, "wait for commit done returned %d\n", ret);

		SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state, ret, SDE_EVTLOG_ERROR);

		ret = -EINVAL;

		goto end;

	}



	sde_encoder_irq_control(drm_enc, false);



skip_wait:

	SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,

		SDE_ENC_RC_STATE_MODESET, SDE_EVTLOG_FUNC_CASE5);
@@ -1920,8 +1906,6 @@ static int _sde_encoder_rc_post_modeset(struct drm_encoder *drm_enc, 
		goto end;

	}



	sde_encoder_irq_control(drm_enc, true);



	_sde_encoder_update_rsc_client(drm_enc, true);



	SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
@@ -2373,6 +2357,9 @@ static void sde_encoder_virt_mode_set(struct drm_encoder *drm_enc, 
	sde_connector_state_get_mode_info(conn->state, &sde_enc->mode_info);

	sde_encoder_dce_set_bpp(sde_enc->mode_info, sde_enc->crtc);



	/* cancel delayed off work, if any */

	kthread_cancel_delayed_work_sync(&sde_enc->delayed_off_work);



	/* release resources before seamless mode change */

	ret = sde_encoder_virt_modeset_rc(drm_enc, adj_mode, true);

	if (ret)
@@ -2610,7 +2597,6 @@ static void _sde_encoder_virt_enable_helper(struct drm_encoder *drm_enc) 
				&sde_enc->cur_master->intf_cfg_v1);



	_sde_encoder_update_vsync_source(sde_enc, &sde_enc->disp_info, false);

	sde_encoder_control_te(drm_enc, true);



	memset(&sde_enc->prv_conn_roi, 0, sizeof(sde_enc->prv_conn_roi));

	memset(&sde_enc->cur_conn_roi, 0, sizeof(sde_enc->cur_conn_roi));
@@ -2713,6 +2699,7 @@ void sde_encoder_virt_restore(struct drm_encoder *drm_enc) 
		sde_enc->cur_master->ops.restore(sde_enc->cur_master);



	_sde_encoder_virt_enable_helper(drm_enc);

	sde_encoder_control_te(drm_enc, true);

}



static void sde_encoder_off_work(struct kthread_work *work)
@@ -2735,6 +2722,7 @@ static void sde_encoder_off_work(struct kthread_work *work) 
static void sde_encoder_virt_enable(struct drm_encoder *drm_enc)

{

	struct sde_encoder_virt *sde_enc = NULL;

	bool has_master_enc = false;

	int i, ret = 0;

	struct msm_compression_info *comp_info = NULL;

	struct drm_display_mode *cur_mode = NULL;
@@ -2761,18 +2749,19 @@ static void sde_encoder_virt_enable(struct drm_encoder *drm_enc) 
	SDE_DEBUG_ENC(sde_enc, "\n");

	SDE_EVT32(DRMID(drm_enc), cur_mode->hdisplay, cur_mode->vdisplay);



	sde_enc->cur_master = NULL;

	for (i = 0; i < sde_enc->num_phys_encs; i++) {

		struct sde_encoder_phys *phys = sde_enc->phys_encs[i];



		if (phys && phys->ops.is_master && phys->ops.is_master(phys)) {

			SDE_DEBUG_ENC(sde_enc, "master is now idx %d\n", i);

			sde_enc->cur_master = phys;

			has_master_enc = true;

			break;

		}

	}



	if (!sde_enc->cur_master) {

	if (!has_master_enc) {

		sde_enc->cur_master = NULL;

		SDE_ERROR("virt encoder has no master! num_phys %d\n", i);

		return;

	}
@@ -2794,6 +2783,9 @@ static void sde_encoder_virt_enable(struct drm_encoder *drm_enc) 
		return;

	}



	/* turn off vsync_in to update tear check configuration */

	sde_encoder_control_te(drm_enc, false);



	memset(&sde_enc->cur_master->intf_cfg_v1, 0,

			sizeof(sde_enc->cur_master->intf_cfg_v1));
@@ -2849,6 +2841,7 @@ static void sde_encoder_virt_enable(struct drm_encoder *drm_enc) 
		sde_enc->cur_master->ops.enable(sde_enc->cur_master);



	_sde_encoder_virt_enable_helper(drm_enc);

	sde_encoder_control_te(drm_enc, true);

}



void sde_encoder_virt_reset(struct drm_encoder *drm_enc)

msm/sde/sde_encoder_dce.c

+21 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.

 * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved.

 */
@@ -913,6 +914,26 @@ void sde_encoder_dce_set_bpp(struct msm_mode_info mode_info, 
			sde_crtc->src_bpp, sde_crtc->target_bpp);

}



bool sde_encoder_has_dsc_hw_rev_2(struct sde_encoder_virt *sde_enc)

{

	enum msm_display_compression_type comp_type;

	int i;



	if (!sde_enc)

		return false;



	comp_type = sde_enc->mode_info.comp_info.comp_type;



	if (comp_type != MSM_DISPLAY_COMPRESSION_DSC)

		return false;



	for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)

		if (sde_enc->hw_dsc[i])

			return test_bit(SDE_DSC_HW_REV_1_2, &sde_enc->hw_dsc[i]->caps->features);



	return false;

}



void sde_encoder_dce_disable(struct sde_encoder_virt *sde_enc)

{

	enum msm_display_compression_type comp_type;

msm/sde/sde_encoder_dce.h

+7 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.

 * Copyright (c) 2016-2017, 2020 The Linux Foundation. All rights reserved.

 */
@@ -36,4 +37,10 @@ int sde_encoder_dce_setup(struct sde_encoder_virt *sde_enc, 
 */

void sde_encoder_dce_flush(struct sde_encoder_virt *sde_enc);



/**

 * sde_encoder_has_dsc_hw_rev_2 :checks if dsc_hw_rev_1_2 feature is enabled

 * @sde_enc: pointer to virtual encoder structure

 */

bool sde_encoder_has_dsc_hw_rev_2(struct sde_encoder_virt *sde_enc);



#endif /* __SDE_ENCODER_DCE_H__ */