Loading msm/dsi/dsi_catalog.c +2 −0 Original line number Diff line number Diff line // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved. * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. */ #include <linux/errno.h> Loading Loading @@ -293,6 +294,7 @@ static void dsi_catalog_phy_4_0_init(struct dsi_phy_hw *phy) dsi_phy_hw_v4_0_cache_phy_timings; phy->ops.set_continuous_clk = dsi_phy_hw_v4_0_set_continuous_clk; phy->ops.commit_phy_timing = dsi_phy_hw_v4_0_commit_phy_timing; phy->ops.phy_idle_off = dsi_phy_hw_v4_0_phy_idle_off; } /** Loading msm/dsi/dsi_catalog.h +2 −0 Original line number Diff line number Diff line /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved. * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _DSI_CATALOG_H_ Loading Loading @@ -125,6 +126,7 @@ void dsi_phy_hw_v4_0_reset_clk_en_sel(struct dsi_phy_hw *phy); void dsi_phy_hw_v4_0_set_continuous_clk(struct dsi_phy_hw *phy, bool enable); void dsi_phy_hw_v4_0_commit_phy_timing(struct dsi_phy_hw *phy, struct dsi_phy_per_lane_cfgs *timing); void dsi_phy_hw_v4_0_phy_idle_off(struct dsi_phy_hw *phy); /* DSI controller common ops */ u32 dsi_ctrl_hw_cmn_get_interrupt_status(struct dsi_ctrl_hw *ctrl); Loading msm/dsi/dsi_display.c +6 −0 Original line number Diff line number Diff line Loading @@ -6111,6 +6111,12 @@ int dsi_display_drm_bridge_init(struct dsi_display *display, display->bridge = bridge; priv->bridges[priv->num_bridges++] = &bridge->base; if (display->tx_cmd_buf == NULL) { rc = dsi_host_alloc_cmd_tx_buffer(display); if (rc) DSI_ERR("failed to allocate cmd tx buffer memory\n"); } error: mutex_unlock(&display->display_lock); return rc; Loading msm/dsi/dsi_phy.c +3 −0 Original line number Diff line number Diff line // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. */ #include <linux/of_device.h> Loading Loading @@ -356,6 +357,8 @@ static int dsi_phy_settings_init(struct platform_device *pdev, phy->allow_phy_power_off = of_property_read_bool(pdev->dev.of_node, "qcom,panel-allow-phy-poweroff"); phy->hw.clamp_enable = of_property_read_bool(pdev->dev.of_node, "qcom,phy-clamp-enable"); of_property_read_u32(pdev->dev.of_node, "qcom,dsi-phy-regulator-min-datarate-bps", Loading msm/dsi/dsi_phy_hw.h +3 −0 Original line number Diff line number Diff line /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved. * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _DSI_PHY_HW_H_ Loading Loading @@ -354,6 +355,7 @@ struct dsi_phy_hw_ops { * @length: Length of the DSI dynamic refresh register base map. * @index: Instance ID of the controller. * @version: DSI PHY version. * @clamp_enable True if phy clamp is enabled * @phy_clamp_base: Base address of phy clamp register map. * @feature_map: Features supported by DSI PHY. * @ops: Function pointer to PHY operations. Loading @@ -366,6 +368,7 @@ struct dsi_phy_hw { u32 index; enum dsi_phy_version version; bool clamp_enable; void __iomem *phy_clamp_base; DECLARE_BITMAP(feature_map, DSI_PHY_MAX_FEATURES); Loading Loading
msm/dsi/dsi_catalog.c +2 −0 Original line number Diff line number Diff line // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved. * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. */ #include <linux/errno.h> Loading Loading @@ -293,6 +294,7 @@ static void dsi_catalog_phy_4_0_init(struct dsi_phy_hw *phy) dsi_phy_hw_v4_0_cache_phy_timings; phy->ops.set_continuous_clk = dsi_phy_hw_v4_0_set_continuous_clk; phy->ops.commit_phy_timing = dsi_phy_hw_v4_0_commit_phy_timing; phy->ops.phy_idle_off = dsi_phy_hw_v4_0_phy_idle_off; } /** Loading
msm/dsi/dsi_catalog.h +2 −0 Original line number Diff line number Diff line /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved. * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _DSI_CATALOG_H_ Loading Loading @@ -125,6 +126,7 @@ void dsi_phy_hw_v4_0_reset_clk_en_sel(struct dsi_phy_hw *phy); void dsi_phy_hw_v4_0_set_continuous_clk(struct dsi_phy_hw *phy, bool enable); void dsi_phy_hw_v4_0_commit_phy_timing(struct dsi_phy_hw *phy, struct dsi_phy_per_lane_cfgs *timing); void dsi_phy_hw_v4_0_phy_idle_off(struct dsi_phy_hw *phy); /* DSI controller common ops */ u32 dsi_ctrl_hw_cmn_get_interrupt_status(struct dsi_ctrl_hw *ctrl); Loading
msm/dsi/dsi_display.c +6 −0 Original line number Diff line number Diff line Loading @@ -6111,6 +6111,12 @@ int dsi_display_drm_bridge_init(struct dsi_display *display, display->bridge = bridge; priv->bridges[priv->num_bridges++] = &bridge->base; if (display->tx_cmd_buf == NULL) { rc = dsi_host_alloc_cmd_tx_buffer(display); if (rc) DSI_ERR("failed to allocate cmd tx buffer memory\n"); } error: mutex_unlock(&display->display_lock); return rc; Loading
msm/dsi/dsi_phy.c +3 −0 Original line number Diff line number Diff line // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. */ #include <linux/of_device.h> Loading Loading @@ -356,6 +357,8 @@ static int dsi_phy_settings_init(struct platform_device *pdev, phy->allow_phy_power_off = of_property_read_bool(pdev->dev.of_node, "qcom,panel-allow-phy-poweroff"); phy->hw.clamp_enable = of_property_read_bool(pdev->dev.of_node, "qcom,phy-clamp-enable"); of_property_read_u32(pdev->dev.of_node, "qcom,dsi-phy-regulator-min-datarate-bps", Loading
msm/dsi/dsi_phy_hw.h +3 −0 Original line number Diff line number Diff line /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved. * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _DSI_PHY_HW_H_ Loading Loading @@ -354,6 +355,7 @@ struct dsi_phy_hw_ops { * @length: Length of the DSI dynamic refresh register base map. * @index: Instance ID of the controller. * @version: DSI PHY version. * @clamp_enable True if phy clamp is enabled * @phy_clamp_base: Base address of phy clamp register map. * @feature_map: Features supported by DSI PHY. * @ops: Function pointer to PHY operations. Loading @@ -366,6 +368,7 @@ struct dsi_phy_hw { u32 index; enum dsi_phy_version version; bool clamp_enable; void __iomem *phy_clamp_base; DECLARE_BITMAP(feature_map, DSI_PHY_MAX_FEATURES); Loading