Loading qcom/sdxlemur-mtp-cpe.dtsi +2 −2 Original line number Diff line number Diff line Loading @@ -45,8 +45,8 @@ <0x218 &apps_smmu 0x0204 0x1>, <0x300 &apps_smmu 0x0207 0x1>, <0x400 &apps_smmu 0x0208 0x1>, <0x500 &apps_smmu 0x020C 0x1>, <0x501 &apps_smmu 0x020E 0x1>; <0x500 &apps_smmu 0x020c 0x1>, <0x501 &apps_smmu 0x020e 0x1>; }; &pcie0_rp { Loading qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi +5 −7 Original line number Diff line number Diff line Loading @@ -31,13 +31,11 @@ iommu-map = <0x0 &apps_smmu 0x0200 0x1>, <0x100 &apps_smmu 0x0201 0x1>, <0x208 &apps_smmu 0x0202 0x1>, <0x210 &apps_smmu 0x0203 0x1>, <0x218 &apps_smmu 0x0204 0x1>, <0x300 &apps_smmu 0x0207 0x1>, <0x400 &apps_smmu 0x0208 0x1>, <0x500 &apps_smmu 0x020C 0x1>, <0x501 &apps_smmu 0x020E 0x1>; <0x210 &apps_smmu 0x0202 0x1>, <0x218 &apps_smmu 0x0203 0x1>, <0x300 &apps_smmu 0x0208 0x1>, <0x400 &apps_smmu 0x020c 0x1>, <0x401 &apps_smmu 0x020e 0x1>; }; &pcie0_rp { Loading Loading
qcom/sdxlemur-mtp-cpe.dtsi +2 −2 Original line number Diff line number Diff line Loading @@ -45,8 +45,8 @@ <0x218 &apps_smmu 0x0204 0x1>, <0x300 &apps_smmu 0x0207 0x1>, <0x400 &apps_smmu 0x0208 0x1>, <0x500 &apps_smmu 0x020C 0x1>, <0x501 &apps_smmu 0x020E 0x1>; <0x500 &apps_smmu 0x020c 0x1>, <0x501 &apps_smmu 0x020e 0x1>; }; &pcie0_rp { Loading
qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi +5 −7 Original line number Diff line number Diff line Loading @@ -31,13 +31,11 @@ iommu-map = <0x0 &apps_smmu 0x0200 0x1>, <0x100 &apps_smmu 0x0201 0x1>, <0x208 &apps_smmu 0x0202 0x1>, <0x210 &apps_smmu 0x0203 0x1>, <0x218 &apps_smmu 0x0204 0x1>, <0x300 &apps_smmu 0x0207 0x1>, <0x400 &apps_smmu 0x0208 0x1>, <0x500 &apps_smmu 0x020C 0x1>, <0x501 &apps_smmu 0x020E 0x1>; <0x210 &apps_smmu 0x0202 0x1>, <0x218 &apps_smmu 0x0203 0x1>, <0x300 &apps_smmu 0x0208 0x1>, <0x400 &apps_smmu 0x020c 0x1>, <0x401 &apps_smmu 0x020e 0x1>; }; &pcie0_rp { Loading