Merge "ARM: dts: msm: update QUPs for sa8195 virtual machine" (f138a340) · Commits · e / devices / android_kernel_fairphone_FP5

qcom/sa8195-qupv3.dtsi

+53 −0

Original line number	Diff line number	Diff line
		@@ -340,6 +340,43 @@
		status = "ok";
		};

		qupv3_se4_4uart: qcom,qup_uart@890000 {
		compatible = "qcom,msm-geni-serial-hs";
		reg = <0x890000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>,
		<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
		<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		pinctrl-names = "default", "active", "sleep";
		pinctrl-0 = <&qupv3_se4_default_ctsrtsrx>,
		<&qupv3_se4_default_tx>;
		pinctrl-1 = <&qupv3_se4_ctsrx>, <&qupv3_se4_rts>,
		<&qupv3_se4_tx>;
		pinctrl-2 = <&qupv3_se4_ctsrx>, <&qupv3_se4_rts>,
		<&qupv3_se4_tx>;
		interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
		qcom,wrapper-core = <&qupv3_0>;
		qcom,wakeup-byte = <0xFD>;
		status = "disabled";
		};

		qupv3_se10_2uart: qcom,qup_uart@a88000 {
		compatible = "qcom,msm-geni-serial-hs";
		reg = <0xa88000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>,
		<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
		<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se10_2uart_active>;
		pinctrl-1 = <&qupv3_se10_2uart_sleep>;
		interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
		};

		/* Debug UART Instance for CDP/MTP platform */
		qupv3_se12_2uart: qcom,qup_uart@0xa90000 {
		compatible = "qcom,msm-geni-console";
		@@ -380,6 +417,22 @@
		status = "disabled";
		};

		qupv3_se16_2uart: qcom,qup_uart@0xa94000 {
		compatible = "qcom,msm-geni-serial-hs";
		reg = <0xa94000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>,
		<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
		<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se16_2uart_active>;
		pinctrl-1 = <&qupv3_se16_2uart_sleep>;
		interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
		};

		/* I2C */
		qupv3_se8_i2c: i2c@a80000 {
		compatible = "qcom,i2c-geni";

qcom/sa8195-vm-lv-lxc.dtsi

+8 −0

Original line number	Diff line number	Diff line
		@@ -30,6 +30,14 @@
		status = "ok";
		};

		&qupv3_se13_4uart {
		status = "ok";
		};

		&qupv3_se4_4uart {
		status = "ok";
		};

		&pcie0_msi {
		status = "ok";
		};

qcom/sdmshrike-pinctrl.dtsi

+67 −0

Original line number	Diff line number	Diff line
		@@ -5013,6 +5013,73 @@
		};
		};

		qupv3_se4_4uart_pins: qupv3_se4_4uart_pins {
		qupv3_se4_default_ctsrtsrx: qupv3_se4_default_ctsrtsrx {
		mux {
		pins = "gpio51", "gpio52", "gpio54";
		function = "gpio";
		};

		config {
		pins = "gpio51", "gpio52", "gpio54";
		drive-strength = <2>;
		bias-pull-down;
		};
		};

		qupv3_se4_default_tx: qupv3_se4_default_tx {
		mux {
		pins = "gpio53";
		function = "gpio";
		};

		config {
		pins = "gpio53";
		drive-strength = <2>;
		bias-pull-up;
		};
		};

		qupv3_se4_ctsrx: qupv3_se4_ctsrx {
		mux {
		pins = "gpio51", "gpio54";
		function = "qup4";
		};

		config {
		pins = "gpio51", "gpio54";
		drive-strength = <2>;
		bias-disable;
		};
		};

		qupv3_se4_rts: qupv3_se4_rts {
		mux {
		pins = "gpio52";
		function = "qup4";
		};

		config {
		pins = "gpio52";
		drive-strength = <2>;
		bias-pull-down;
		};
		};

		qupv3_se4_tx: qupv3_se4_tx {
		mux {
		pins = "gpio53";
		function = "qup4";
		};

		config {
		pins = "gpio53";
		drive-strength = <2>;
		bias-pull-up;
		};
		};
		};

		/* SE 10 pin mappings */
		qupv3_se10_2uart_pins: qupv3_se10_2uart_pins {
		qupv3_se10_2uart_active: qupv3_se10_2uart_active {