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Commit cfa7f9cf authored by Jordan Crouse's avatar Jordan Crouse
Browse files

msm: kgsl: Remove unneeded static inline functions 



Over the years we have really abused inline functions in the driver code.
Remove a chunk of the "functions" that are single use or otherwise
just not worth it.

As a bonus, moving the functions around exposed a single use of some
adreno_reg registers in a3xx that we could get rid of that while we
are mucking about.

Change-Id: Ic0dedbad85df436cbd7e5746964200ee9f87e1a4
Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
parent 41b90d7b

drivers/gpu/msm/adreno.c

+29 −66
Original line number Diff line number Diff line
@@ -168,22 +168,6 @@ unsigned int adreno_get_rptr(struct adreno_ringbuffer *rb) 
	return rptr;

}



/**

 * adreno_of_read_property() - Adreno read property

 * @node: Device node

 *

 * Read a u32 property.

 */

static inline int adreno_of_read_property(struct device *dev,

		struct device_node *node, const char *prop, unsigned int *ptr)

{

	int ret = of_property_read_u32(node, prop, ptr);



	if (ret)

		dev_err(dev, "%pOF: Unable to read '%s'\n", node, prop);

	return ret;

}



static void __iomem *efuse_base;

static size_t efuse_len;
@@ -259,18 +243,6 @@ static int _get_counter(struct adreno_device *adreno_dev, 
	return ret;

}



static inline void _put_counter(struct adreno_device *adreno_dev,

		int group, int countable, unsigned int *lo,

		unsigned int *hi)

{

	if (*lo != 0)

		adreno_perfcounter_put(adreno_dev, group, countable,

			PERFCOUNTER_FLAG_KERNEL);



	*lo = 0;

	*hi = 0;

}



/**

 * adreno_fault_detect_start() - Allocate performance counters

 * used for fast fault detection
@@ -319,11 +291,16 @@ void adreno_fault_detect_stop(struct adreno_device *adreno_dev) 
		return;



	for (i = 0; i < gpudev->ft_perf_counters_count; i++) {

		_put_counter(adreno_dev, gpudev->ft_perf_counters[i].counter,

		if (!adreno_ft_regs[j + (i * 2)])

			continue;



		adreno_perfcounter_put(adreno_dev,

			gpudev->ft_perf_counters[i].counter,

			gpudev->ft_perf_counters[i].countable,

			 &adreno_ft_regs[j + (i * 2)],

			 &adreno_ft_regs[j + ((i * 2) + 1)]);

			PERFCOUNTER_FLAG_KERNEL);



		adreno_ft_regs[j + (i * 2)] = 0;

		adreno_ft_regs[(j + (i * 2)) + 1] = 0;

	}



	adreno_dev->fast_hang_detect = 0;
@@ -921,8 +898,11 @@ static int adreno_of_parse_pwrlevels(struct adreno_device *adreno_dev, 
		unsigned int index;

		struct kgsl_pwrlevel *level;



		if (adreno_of_read_property(device->dev, child, "reg", &index))

		if (of_property_read_u32(child, "reg", &index)) {

			dev_err(device->dev,

				"%pOF: powerlevel index not found\n", child);

			return -EINVAL;

		}



		if (index >= KGSL_MAX_PWRLEVELS) {

			dev_err(device->dev,
@@ -936,9 +916,12 @@ static int adreno_of_parse_pwrlevels(struct adreno_device *adreno_dev, 


		level = &pwr->pwrlevels[index];



		if (adreno_of_read_property(device->dev, child, "qcom,gpu-freq",

			&level->gpu_freq))

		if (of_property_read_u32(child, "qcom,gpu-freq",

			&level->gpu_freq)) {

			dev_err(device->dev,

				"%pOF: Unable to read qcom,gpu-freq\n", child);

			return -EINVAL;

		}



		of_property_read_u32(child, "qcom,acd-level",

			&level->acd_level);
@@ -2227,27 +2210,6 @@ static int adreno_stop(struct kgsl_device *device) 
	return error;

}



static inline bool adreno_try_soft_reset(struct kgsl_device *device, int fault)

{

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);



	/*

	 * Do not do soft reset for a IOMMU fault (because the IOMMU hardware

	 * needs a reset too) and also for below gpu

	 * A304: It can't do SMMU programming of any kind after a soft reset

	 * A612: IPC protocol between RGMU and CP will not restart after reset

	 * A610: An across chip issue with reset line in all 11nm chips,

	 * resulting in recommendation to not use soft reset

	 */



	if ((fault & ADRENO_IOMMU_PAGE_FAULT) || adreno_is_a304(adreno_dev) ||

			adreno_is_a612(adreno_dev) ||

			adreno_is_a610(adreno_dev))

		return false;



	return true;

}



/**

 * adreno_reset() - Helper function to reset the GPU

 * @device: Pointer to the KGSL device structure for the GPU
@@ -2263,8 +2225,14 @@ int adreno_reset(struct kgsl_device *device, int fault) 
	int ret = -EINVAL;

	int i = 0;



	/* Try soft reset first */

	if (adreno_try_soft_reset(device, fault)) {

	/*

	 * Try soft reset first Do not do soft reset for a IOMMU fault (because

	 * the IOMMU hardware needs a reset too) or for the A304 because it

	 * can't do SMMU programming of any kind after a soft reset

	 */



	if (!(fault & ADRENO_IOMMU_PAGE_FAULT) && !adreno_is_a304(adreno_dev)

		&& !adreno_is_a612(adreno_dev) && !adreno_is_a610(adreno_dev)) {

		/* Make sure VBIF is cleared before resetting */

		ret = adreno_clear_pending_transactions(device);
@@ -3514,12 +3482,6 @@ static void adreno_device_private_destroy(struct kgsl_device_private *dev_priv) 
	kfree(adreno_priv);

}



static inline s64 adreno_ticks_to_us(u32 ticks, u32 freq)

{

	freq /= 1000000;

	return ticks / freq;

}



/**

 * adreno_power_stats() - Reads the counters needed for freq decisions

 * @device: Pointer to device whose counters are read
@@ -3556,8 +3518,9 @@ static void adreno_power_stats(struct kgsl_device *device, 
		do_div(stats->busy_time, 192);

	} else {

		/* clock sourced from GFX3D */

		stats->busy_time = adreno_ticks_to_us(gpu_busy,

			kgsl_pwrctrl_active_freq(pwr));

		s64 freq = kgsl_pwrctrl_active_freq(pwr) / 1000000;



		stats->busy_time = gpu_busy / freq;

	}



	if (device->pwrctrl.bus_control) {

drivers/gpu/msm/adreno.h

+0 −4
Original line number Diff line number Diff line
@@ -594,10 +594,7 @@ struct adreno_drawobj_profile_entry { 
 * and are indexed by the enumeration values defined in this enum

 */

enum adreno_regs {

	ADRENO_REG_CP_ME_RAM_WADDR,

	ADRENO_REG_CP_ME_RAM_DATA,

	ADRENO_REG_CP_PFP_UCODE_DATA,

	ADRENO_REG_CP_PFP_UCODE_ADDR,

	ADRENO_REG_CP_RB_BASE,

	ADRENO_REG_CP_RB_BASE_HI,

	ADRENO_REG_CP_RB_RPTR_ADDR_LO,
@@ -616,7 +613,6 @@ enum adreno_regs { 
	ADRENO_REG_CP_TIMESTAMP,

	ADRENO_REG_CP_SCRATCH_REG6,

	ADRENO_REG_CP_SCRATCH_REG7,

	ADRENO_REG_CP_ME_RAM_RADDR,

	ADRENO_REG_CP_ROQ_ADDR,

	ADRENO_REG_CP_ROQ_DATA,

	ADRENO_REG_CP_MEQ_ADDR,

drivers/gpu/msm/adreno_a3xx.c

+16 −57
Original line number Diff line number Diff line
@@ -660,12 +660,11 @@ static int a3xx_send_me_init(struct adreno_device *adreno_dev, 
	return ret;

}



static int a3xx_microcode_load(struct adreno_device *adreno_dev);

static void a3xx_microcode_load(struct adreno_device *adreno_dev);



static int a3xx_rb_start(struct adreno_device *adreno_dev)

{

	struct adreno_ringbuffer *rb = ADRENO_CURRENT_RINGBUFFER(adreno_dev);

	int ret;



	/*

	 * The size of the ringbuffer in the hardware is the log2
@@ -681,15 +680,12 @@ static int a3xx_rb_start(struct adreno_device *adreno_dev) 
	adreno_writereg(adreno_dev, ADRENO_REG_CP_RB_BASE,

			rb->buffer_desc.gpuaddr);



	ret = a3xx_microcode_load(adreno_dev);

	if (ret == 0) {

	a3xx_microcode_load(adreno_dev);



	/* clear ME_HALT to start micro engine */

	adreno_writereg(adreno_dev, ADRENO_REG_CP_ME_CNTL, 0);



		ret = a3xx_send_me_init(adreno_dev, rb);

	}



	return ret;

	return a3xx_send_me_init(adreno_dev, rb);

}



/*
@@ -1200,10 +1196,6 @@ static unsigned int a3xx_int_bits[ADRENO_INT_BITS_MAX] = { 


/* Register offset defines for A3XX */

static unsigned int a3xx_register_offsets[ADRENO_REG_REGISTER_MAX] = {

	ADRENO_REG_DEFINE(ADRENO_REG_CP_ME_RAM_WADDR, A3XX_CP_ME_RAM_WADDR),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_ME_RAM_DATA, A3XX_CP_ME_RAM_DATA),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_PFP_UCODE_DATA, A3XX_CP_PFP_UCODE_DATA),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_PFP_UCODE_ADDR, A3XX_CP_PFP_UCODE_ADDR),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_BASE, A3XX_CP_RB_BASE),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_BASE_HI, ADRENO_REG_SKIP),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_RPTR, A3XX_CP_RB_RPTR),
@@ -1220,7 +1212,6 @@ static unsigned int a3xx_register_offsets[ADRENO_REG_REGISTER_MAX] = { 
	ADRENO_REG_DEFINE(ADRENO_REG_CP_TIMESTAMP, A3XX_CP_SCRATCH_REG0),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_SCRATCH_REG6, A3XX_CP_SCRATCH_REG6),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_SCRATCH_REG7, A3XX_CP_SCRATCH_REG7),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_ME_RAM_RADDR, A3XX_CP_ME_RAM_RADDR),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_ROQ_ADDR, A3XX_CP_ROQ_ADDR),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_ROQ_DATA, A3XX_CP_ROQ_DATA),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_MEQ_ADDR, A3XX_CP_MEQ_ADDR),
@@ -1355,57 +1346,25 @@ static int a3xx_microcode_read(struct adreno_device *adreno_dev) 


	return 0;

}

/**

 * load_pm4_ucode() - Load pm4 ucode

 * @adreno_dev: Pointer to an adreno device

 * @start: Starting index in pm4 ucode to load

 * @end: Ending index of pm4 ucode to load

 * @addr: Address to load the pm4 ucode

 *

 * Load the pm4 ucode from @start at @addr.

 */

static inline void load_pm4_ucode(struct adreno_device *adreno_dev,

			unsigned int start, unsigned int end, unsigned int addr)

{

	int i;



	adreno_writereg(adreno_dev, ADRENO_REG_CP_ME_RAM_WADDR, addr);

	for (i = start; i < end; i++)

		adreno_writereg(adreno_dev, ADRENO_REG_CP_ME_RAM_DATA,

				adreno_dev->fw[ADRENO_FW_PM4].fwvirt[i]);

}

/**

 * load_pfp_ucode() - Load pfp ucode

 * @adreno_dev: Pointer to an adreno device

 * @start: Starting index in pfp ucode to load

 * @end: Ending index of pfp ucode to load

 * @addr: Address to load the pfp ucode

 *

 * Load the pfp ucode from @start at @addr.

 */

static inline void load_pfp_ucode(struct adreno_device *adreno_dev,

			unsigned int start, unsigned int end, unsigned int addr)

{

	int i;



	adreno_writereg(adreno_dev, ADRENO_REG_CP_PFP_UCODE_ADDR, addr);

	for (i = start; i < end; i++)

		adreno_writereg(adreno_dev, ADRENO_REG_CP_PFP_UCODE_DATA,

				adreno_dev->fw[ADRENO_FW_PFP].fwvirt[i]);

}



static int a3xx_microcode_load(struct adreno_device *adreno_dev)

static void a3xx_microcode_load(struct adreno_device *adreno_dev)

{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	size_t pm4_size = adreno_dev->fw[ADRENO_FW_PM4].size;

	size_t pfp_size = adreno_dev->fw[ADRENO_FW_PFP].size;

	int i;



	/* load the CP ucode using AHB writes */

	load_pm4_ucode(adreno_dev, 1, pm4_size, 0);

	kgsl_regwrite(device, A3XX_CP_ME_RAM_WADDR, 0);



	/* load the prefetch parser ucode using AHB writes */

	load_pfp_ucode(adreno_dev, 1, pfp_size, 0);

	for (i = 1; i < pm4_size; i++)

		kgsl_regwrite(device, A3XX_CP_ME_RAM_DATA,

			adreno_dev->fw[ADRENO_FW_PM4].fwvirt[i]);



	return 0;

	kgsl_regwrite(device, A3XX_CP_PFP_UCODE_ADDR, 0);

	for (i = 1; i < pfp_size; i++)

		kgsl_regwrite(device, A3XX_CP_PFP_UCODE_DATA,

			adreno_dev->fw[ADRENO_FW_PFP].fwvirt[i]);

}



static void a3xx_clk_set_options(struct adreno_device *adreno_dev,

drivers/gpu/msm/adreno_a6xx.c

+1 −1
Original line number Diff line number Diff line
@@ -938,7 +938,7 @@ static int _load_firmware(struct kgsl_device *device, const char *fwfile, 
 * @adreno_dev: Pointer to the adreno device that has the GMU

 * @state: State to set: true is ON, false is OFF

 */

static inline void a6xx_gpu_keepalive(struct adreno_device *adreno_dev,

static void a6xx_gpu_keepalive(struct adreno_device *adreno_dev,

		bool state)

{

	if (!gmu_core_isenabled(KGSL_DEVICE(adreno_dev)))

drivers/gpu/msm/adreno_a6xx_gmu.c

+1 −1
Original line number Diff line number Diff line
@@ -609,7 +609,7 @@ static int a6xx_gmu_oob_set(struct kgsl_device *device, 
 * @device: Pointer to the kgsl device that has the GMU

 * @req: Which of the OOB bits to clear

 */

static inline void a6xx_gmu_oob_clear(struct kgsl_device *device,

static void a6xx_gmu_oob_clear(struct kgsl_device *device,

		enum oob_request req)

{

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);