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Commit 41b90d7b authored by Jordan Crouse's avatar Jordan Crouse
Browse files

msm: kgsl: Remove a few unused device tree properties 



Remove some unneeded device tree properties. qcom,id is not
used anywhere (and is always zero).  The label name is
redundant since the platform device already has a name.

The idle-timeout is 80 ms on all targets and the snapshot
size and high bank bit are GPU target specific and can be
moved to the GPU list instead.

Change-Id: Ic0dedbadb3848b844f4742c7417cfdf9bb4ca575
Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
parent 12d67a7d

drivers/gpu/msm/adreno-gpulist.h

+38 −0
Original line number Diff line number Diff line
@@ -30,6 +30,7 @@ static const struct adreno_a3xx_core adreno_gpu_core_a306 = { 
		.gmem_size = SZ_128K,

		.busy_mask = 0x7ffffffe,

		.bus_width = 0,

		.snapshot_size = 600 * SZ_1K,

	},

	.pm4fw_name = "a300_pm4.fw",

	.pfpfw_name = "a300_pfp.fw",
@@ -52,6 +53,7 @@ static const struct adreno_a3xx_core adreno_gpu_core_a306a = { 
		.gmem_size = SZ_128K,

		.busy_mask = 0x7ffffffe,

		.bus_width = 16,

		.snapshot_size = 600 * SZ_1K,

	},

	.pm4fw_name = "a300_pm4.fw",

	.pfpfw_name = "a300_pfp.fw",
@@ -72,6 +74,7 @@ static const struct adreno_a3xx_core adreno_gpu_core_a304 = { 
		.gmem_size = (SZ_64K + SZ_32K),

		.busy_mask = 0x7ffffffe,

		.bus_width = 0,

		.snapshot_size = 600 * SZ_1K,

	},

	.pm4fw_name = "a300_pm4.fw",

	.pfpfw_name = "a300_pfp.fw",
@@ -196,6 +199,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a530v2 = { 
		.gmem_size = SZ_1M,

		.busy_mask = 0xfffffffe,

		.bus_width = 32,

		.snapshot_size = SZ_1M,

	},

	.gpmu_tsens = 0x00060007,

	.max_power = 5448,
@@ -208,6 +212,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a530v2 = { 
	.hwcg_count = ARRAY_SIZE(a530_hwcg_regs),

	.vbif = a530_vbif_regs,

	.vbif_count = ARRAY_SIZE(a530_vbif_regs),

	.highest_bank_bit = 15,

};



static const struct adreno_a5xx_core adreno_gpu_core_a530v3 = {
@@ -221,6 +226,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a530v3 = { 
		.gmem_size = SZ_1M,

		.busy_mask = 0xfffffffe,

		.bus_width = 32,

		.snapshot_size = SZ_1M,

	},

	.gpmu_tsens = 0x00060007,

	.max_power = 5448,
@@ -233,6 +239,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a530v3 = { 
	.hwcg_count = ARRAY_SIZE(a530_hwcg_regs),

	.vbif = a530_vbif_regs,

	.vbif_count = ARRAY_SIZE(a530_vbif_regs),

	.highest_bank_bit = 15,

};



/* For a505, a506 and a508 */
@@ -286,6 +293,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a505 = { 
		.gmem_size = (SZ_128K + SZ_8K),

		.busy_mask = 0xfffffffe,

		.bus_width = 16,

		.snapshot_size = SZ_1M,

	},

	.pm4fw_name = "a530_pm4.fw",

	.pfpfw_name = "a530_pfp.fw",
@@ -305,6 +313,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a506 = { 
		.gmem_size = (SZ_128K + SZ_8K),

		.busy_mask = 0xfffffffe,

		.bus_width = 16,

		.snapshot_size = SZ_1M,

	},

	.pm4fw_name = "a530_pm4.fw",

	.pfpfw_name = "a530_pfp.fw",
@@ -313,6 +322,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a506 = { 
	.hwcg_count = ARRAY_SIZE(a50x_hwcg_regs),

	.vbif = a530_vbif_regs,

	.vbif_count = ARRAY_SIZE(a530_vbif_regs),

	.highest_bank_bit = 14,

};



static const struct adreno_reglist a510_hwcg_regs[] = {
@@ -382,6 +392,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a510 = { 
		.gmem_size = SZ_256K,

		.busy_mask = 0xfffffffe,

		.bus_width = 16,

		.snapshot_size = SZ_1M,

	},

	.pm4fw_name = "a530_pm4.fw",

	.pfpfw_name = "a530_pfp.fw",
@@ -507,6 +518,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a540v2 = { 
		.gmem_size = SZ_1M,

		.busy_mask = 0xfffffffe,

		.bus_width = 32,

		.snapshot_size = SZ_1M,

	},

	.gpmu_tsens = 0x000c000d,

	.max_power = 5448,
@@ -518,6 +530,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a540v2 = { 
	.hwcg_count = ARRAY_SIZE(a540_hwcg_regs),

	.vbif = a540_vbif_regs,

	.vbif_count = ARRAY_SIZE(a540_vbif_regs),

	.highest_bank_bit = 15,

};



static const struct adreno_reglist a512_hwcg_regs[] = {
@@ -589,12 +602,14 @@ static const struct adreno_a5xx_core adreno_gpu_core_a512 = { 
		.gmem_size = (SZ_256K + SZ_16K),

		.busy_mask = 0xfffffffe,

		.bus_width = 32,

		.snapshot_size = SZ_1M,

	},

	.pm4fw_name = "a530_pm4.fw",

	.pfpfw_name = "a530_pfp.fw",

	.zap_name = "a512_zap",

	.hwcg = a512_hwcg_regs,

	.hwcg_count = ARRAY_SIZE(a512_hwcg_regs),

	.highest_bank_bit = 14,

};



static const struct adreno_a5xx_core adreno_gpu_core_a508 = {
@@ -607,6 +622,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a508 = { 
		.gmem_size = (SZ_128K + SZ_8K),

		.busy_mask = 0xfffffffe,

		.bus_width = 32,

		.snapshot_size = SZ_1M,

	},

	.pm4fw_name = "a530_pm4.fw",

	.pfpfw_name = "a530_pfp.fw",
@@ -615,6 +631,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a508 = { 
	.hwcg_count = ARRAY_SIZE(a50x_hwcg_regs),

	.vbif = a530_vbif_regs,

	.vbif_count = ARRAY_SIZE(a530_vbif_regs),

	.highest_bank_bit = 14,

};



DEFINE_DEPRECATED_CORE(a630v1, ADRENO_REV_A630, 6, 3, 0, 0);
@@ -781,6 +798,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a630v2 = { 
		.gmem_size = SZ_1M,

		.busy_mask = 0xfffffffe,

		.bus_width = 32,

		.snapshot_size = SZ_1M,

	},

	.prim_fifo_threshold = 0x0018000,

	.pdc_address_offset = 0x00030080,
@@ -795,6 +813,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a630v2 = { 
	.vbif_count = ARRAY_SIZE(a630_vbif_regs),

	.hang_detect_cycles = 0xcfffff,

	.protected_regs = a630_protected_regs,

	.highest_bank_bit = 15,

};



/* For a615, a616 and a618 */
@@ -880,6 +899,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a615 = { 
		.gmem_size = SZ_512K,

		.busy_mask = 0xfffffffe,

		.bus_width = 32,

		.snapshot_size = 600 * SZ_1K,

	},

	.prim_fifo_threshold = 0x0018000,

	.pdc_address_offset = 0x00030080,
@@ -894,6 +914,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a615 = { 
	.vbif_count = ARRAY_SIZE(a615_gbif_regs),

	.hang_detect_cycles = 0xcfffff,

	.protected_regs = a630_protected_regs,

	.highest_bank_bit = 14,

};



static const struct adreno_a6xx_core adreno_gpu_core_a618 = {
@@ -907,6 +928,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a618 = { 
		.gmem_size = SZ_512K,

		.busy_mask = 0xfffffffe,

		.bus_width = 32,

		.snapshot_size = SZ_1M,

	},

	.prim_fifo_threshold = 0x0018000,

	.pdc_address_offset = 0x00030090,
@@ -921,6 +943,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a618 = { 
	.vbif_count = ARRAY_SIZE(a615_gbif_regs),

	.hang_detect_cycles = 0x3fffff,

	.protected_regs = a630_protected_regs,

	.highest_bank_bit = 14,

};



static const struct adreno_reglist a620_hwcg_regs[] = {
@@ -1035,6 +1058,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a620 = { 
		.gmem_size = SZ_512K,

		.busy_mask = 0xfffffffe,

		.bus_width = 32,

		.snapshot_size = 2 * SZ_1M,

	},

	.prim_fifo_threshold = 0x0010000,

	.pdc_address_offset = 0x000300a0,
@@ -1051,6 +1075,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a620 = { 
	.hang_detect_cycles = 0x3ffff,

	.protected_regs = a620_protected_regs,

	.disable_tseskip = true,

	.highest_bank_bit = 14,

};



static const struct adreno_reglist a640_hwcg_regs[] = {
@@ -1125,6 +1150,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a640 = { 
		.gmem_size = SZ_1M, //Verified 1MB

		.busy_mask = 0xfffffffe,

		.bus_width = 32,

		.snapshot_size = 2 * SZ_1M,

	},

	.prim_fifo_threshold = 0x00200000,

	.pdc_address_offset = 0x00030090,
@@ -1140,6 +1166,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a640 = { 
	.hang_detect_cycles = 0xcfffff,

	.protected_regs = a630_protected_regs,

	.disable_tseskip = true,

	.highest_bank_bit = 15,

};



static const struct adreno_reglist a650_hwcg_regs[] = {
@@ -1205,6 +1232,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a650 = { 
		.gmem_size = SZ_1M + SZ_128K, /* verified 1152kB */

		.busy_mask = 0xfffffffe,

		.bus_width = 32,

		.snapshot_size = 2 * SZ_1M,

	},

	.prim_fifo_threshold = 0x00300000,

	.pdc_address_offset = 0x000300A0,
@@ -1220,6 +1248,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a650 = { 
	.hang_detect_cycles = 0xcfffff,

	.protected_regs = a620_protected_regs,

	.disable_tseskip = true,

	.highest_bank_bit = 16,

};



static const struct adreno_a6xx_core adreno_gpu_core_a650v2 = {
@@ -1234,6 +1263,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a650v2 = { 
		.gmem_size = SZ_1M + SZ_128K, /* verified 1152kB */

		.busy_mask = 0xfffffffe,

		.bus_width = 32,

		.snapshot_size = 2 * SZ_1M,

	},

	.prim_fifo_threshold = 0x00300000,

	.pdc_address_offset = 0x000300A0,
@@ -1249,6 +1279,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a650v2 = { 
	.hang_detect_cycles = 0x3ffff,

	.protected_regs = a620_protected_regs,

	.disable_tseskip = true,

	.highest_bank_bit = 16,

};



static const struct adreno_a6xx_core adreno_gpu_core_a680 = {
@@ -1260,6 +1291,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a680 = { 
		.gmem_size = SZ_2M,

		.busy_mask = 0xfffffffe,

		.bus_width = 32,

		.snapshot_size = SZ_1M,

	},

	.prim_fifo_threshold = 0x00400000,

	.pdc_address_offset = 0x00030090,
@@ -1275,6 +1307,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a680 = { 
	.hang_detect_cycles = 0xcfffff,

	.protected_regs = a630_protected_regs,

	.disable_tseskip = true,

	.highest_bank_bit = 16,

};



static const struct adreno_reglist a612_hwcg_regs[] = {
@@ -1337,6 +1370,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a612 = { 
		.gmem_size = (SZ_128K + SZ_4K),

		.busy_mask = 0xfffffffe,

		.bus_width = 32,

		.snapshot_size = SZ_1M,

	},

	.prim_fifo_threshold = 0x00080000,

	.pdc_address_offset = 0x00030080,
@@ -1349,6 +1383,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a612 = { 
	.vbif_count = ARRAY_SIZE(a640_vbif_regs),

	.hang_detect_cycles = 0x3fffff,

	.protected_regs = a630_protected_regs,

	.highest_bank_bit = 14,

};



static const struct adreno_a6xx_core adreno_gpu_core_a616 = {
@@ -1362,6 +1397,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a616 = { 
		.gmem_size = SZ_512K,

		.busy_mask = 0xfffffffe,

		.bus_width = 32,

		.snapshot_size = SZ_1M,

	},

	.prim_fifo_threshold = 0x0018000,

	.pdc_address_offset = 0x00030080,
@@ -1376,6 +1412,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a616 = { 
	.vbif_count = ARRAY_SIZE(a615_gbif_regs),

	.hang_detect_cycles = 0xcfffff,

	.protected_regs = a630_protected_regs,

	.highest_bank_bit = 14,

};



static const struct adreno_a6xx_core adreno_gpu_core_a610 = {
@@ -1398,6 +1435,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a610 = { 
	.vbif_count = ARRAY_SIZE(a640_vbif_regs),

	.hang_detect_cycles = 0x3ffff,

	.protected_regs = a630_protected_regs,

	.highest_bank_bit = 14,

};



static const struct adreno_gpu_core *adreno_gpulist[] = {

drivers/gpu/msm/adreno.c

+17 −17
Original line number Diff line number Diff line
@@ -46,9 +46,6 @@ static struct adreno_device device_3d0 = { 
		.pwrscale = KGSL_PWRSCALE_INIT(&adreno_tz_data),

		.name = DEVICE_3D0_NAME,

		.id = 0,

		.pwrctrl = {

			.irq_name = "kgsl_3d0_irq",

		},

		.iomemname = "kgsl_3d0_reg_memory",

		.ftbl = &adreno_functable,

	},
@@ -1109,15 +1106,6 @@ static int adreno_of_get_power(struct adreno_device *adreno_dev, 
	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	struct device_node *node = pdev->dev.of_node;

	struct resource *res;

	unsigned int timeout;



	if (of_property_read_string(node, "label", &pdev->name)) {

		dev_err(device->dev, "Unable to read 'label'\n");

		return -EINVAL;

	}



	if (adreno_of_read_property(device->dev, node, "qcom,id", &pdev->id))

		return -EINVAL;



	/* Get starting physical address of device registers */

	res = platform_get_resource_byname(device->pdev, IORESOURCE_MEM,
@@ -1144,10 +1132,8 @@ static int adreno_of_get_power(struct adreno_device *adreno_dev, 


	l3_pwrlevel_probe(device, node);



	if (of_property_read_u32(node, "qcom,idle-timeout", &timeout))

		timeout = 80;



	device->pwrctrl.interval_timeout = msecs_to_jiffies(timeout);

	/* Default timeout is 80 ms across all targets */

	device->pwrctrl.interval_timeout = msecs_to_jiffies(80);



	device->pwrctrl.bus_control = of_property_read_bool(node,

		"qcom,bus-control");
@@ -1345,6 +1331,7 @@ static int adreno_probe(struct platform_device *pdev) 
	struct kgsl_device *device;

	int status;

	unsigned int priv;

	u32 size;



	of_id = of_match_device(adreno_match_table, &pdev->dev);

	if (!of_id)
@@ -1441,6 +1428,19 @@ static int adreno_probe(struct platform_device *pdev) 
	if (status)

		goto out;



	/* Initialize the snapshot engine */

	size = adreno_dev->gpucore->snapshot_size;



	/*

	 * Use a default size if one wasn't specified, but print a warning so

	 * the developer knows to fix it

	 */



	if (WARN(!size, "The snapshot size was not specified in the gpucore\n"))

		size = SZ_1M;



	kgsl_device_snapshot_probe(device, size);



	status = adreno_ringbuffer_probe(adreno_dev);

	if (status)

		goto out;
@@ -3790,7 +3790,7 @@ static struct platform_driver adreno_platform_driver = { 
	.resume = kgsl_resume_driver,

	.id_table = adreno_id_table,

	.driver = {

		.name = DEVICE_3D_NAME,

		.name = "kgsl-3d",

		.pm = &kgsl_pm_ops,

		.of_match_table = adreno_match_table,

	}

drivers/gpu/msm/adreno.h

+2 −1
Original line number Diff line number Diff line
@@ -13,7 +13,6 @@ 
#include "adreno_ringbuffer.h"

#include "kgsl_sharedmem.h"



#define DEVICE_3D_NAME "kgsl-3d"

#define DEVICE_3D0_NAME "kgsl-3d0"



/* ADRENO_DEVICE - Given a kgsl_device return the adreno device struct */
@@ -363,6 +362,8 @@ struct adreno_gpu_core { 
	size_t gmem_size;

	unsigned int busy_mask;

	u32 bus_width;

	/** @snapshot_size: Size of the static snapshot region in bytes */

	u32 snapshot_size;

};



/**

drivers/gpu/msm/adreno_a5xx.c

+3 −12
Original line number Diff line number Diff line
@@ -210,21 +210,13 @@ static int a5xx_critical_packet_construct(struct adreno_device *adreno_dev) 


static void a5xx_init(struct adreno_device *adreno_dev)

{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);



	of_property_read_u32(device->pdev->dev.of_node,

		"qcom,highest-bank-bit", &adreno_dev->highest_bank_bit);



	if (WARN(adreno_dev->highest_bank_bit < 13 ||

			adreno_dev->highest_bank_bit > 16,

			"The highest-bank-bit property is invalid\n"))

		adreno_dev->highest_bank_bit =

			clamp_t(unsigned int, adreno_dev->highest_bank_bit,

				13, 16);

	const struct adreno_a5xx_core *a5xx_core = to_a5xx_core(adreno_dev);



	if (ADRENO_FEATURE(adreno_dev, ADRENO_GPMU))

		INIT_WORK(&adreno_dev->gpmu_work, a5xx_gpmu_reset);



	adreno_dev->highest_bank_bit = a5xx_core->highest_bank_bit;



	INIT_WORK(&adreno_dev->irq_storm_work, a5xx_irq_storm_worker);



	if (ADRENO_QUIRK(adreno_dev, ADRENO_QUIRK_CRITICAL_PACKETS)) {
@@ -1557,7 +1549,6 @@ static void a5xx_start(struct adreno_device *adreno_dev) 
	kgsl_regwrite(device, A5XX_RBBM_AHB_CNTL2, 0x0000003F);

	bit = adreno_dev->highest_bank_bit ?

		(adreno_dev->highest_bank_bit - 13) & 0x03 : 0;



	/*

	 * Program the highest DDR bank bit that was passed in

	 * from the DT in a handful of registers. Some of these

drivers/gpu/msm/adreno_a5xx.h

+2 −0
Original line number Diff line number Diff line
@@ -36,6 +36,8 @@ struct adreno_a5xx_core { 
	const struct adreno_reglist *vbif;

	/** @vbif_count: Number of registers in @vbif */

	u32 vbif_count;

	/** @highest_bank_bit: The bit of the highest DDR bank */

	u32 highest_bank_bit;

};



#define A5XX_CP_CTXRECORD_MAGIC_REF     0x27C4BAFCUL