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Commit cd3079ef authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "mhi: core: move certain logs to controller log buffer"

parents 8410be1f 79730055

drivers/bus/mhi/controllers/mhi_arch_qcom.c

+46 −39
Original line number Diff line number Diff line
@@ -40,16 +40,18 @@ struct arch_info { 
#define DLOG "Dev->Host: "

#define HLOG "Host: "



#define MHI_TSYNC_LOG_PAGES (10)

#define MHI_TSYNC_LOG_PAGES (2)



#ifdef CONFIG_MHI_DEBUG



#define MHI_IPC_LOG_PAGES (100)

#define MHI_CNTRL_LOG_PAGES (25)

enum MHI_DEBUG_LEVEL  mhi_ipc_log_lvl = MHI_MSG_LVL_VERBOSE;



#else



#define MHI_IPC_LOG_PAGES (10)

#define MHI_CNTRL_LOG_PAGES (5)

enum MHI_DEBUG_LEVEL  mhi_ipc_log_lvl = MHI_MSG_LVL_ERROR;



#endif
@@ -146,7 +148,7 @@ static void mhi_arch_pci_link_state_cb(struct msm_pcie_notify *notify) 


	switch (notify->event) {

	case MSM_PCIE_EVENT_WAKEUP:

		MHI_LOG("Received MSM_PCIE_EVENT_WAKE signal\n");

		MHI_CNTRL_LOG("Received PCIE_WAKE signal\n");



		/* bring link out of d3cold */

		if (mhi_dev->powered_on) {
@@ -155,14 +157,14 @@ static void mhi_arch_pci_link_state_cb(struct msm_pcie_notify *notify) 
		}

		break;

	case MSM_PCIE_EVENT_L1SS_TIMEOUT:

		MHI_VERB("Received MSM_PCIE_EVENT_L1SS_TIMEOUT signal\n");

		MHI_VERB("Received PCIE_L1SS_TIMEOUT signal\n");



		pm_runtime_mark_last_busy(&pci_dev->dev);

		pm_request_autosuspend(&pci_dev->dev);

		break;

	case MSM_PCIE_EVENT_DRV_CONNECT:

		/* drv is connected we can suspend now */

		MHI_LOG("Received MSM_PCIE_EVENT_DRV_CONNECT signal\n");

		MHI_CNTRL_LOG("Received DRV_CONNECT signal\n");



		arch_info->drv_connected = true;
@@ -177,7 +179,7 @@ static void mhi_arch_pci_link_state_cb(struct msm_pcie_notify *notify) 
		mutex_unlock(&mhi_cntrl->pm_mutex);

		break;

	case MSM_PCIE_EVENT_DRV_DISCONNECT:

		MHI_LOG("Received MSM_PCIE_EVENT_DRV_DISCONNECT signal\n");

		MHI_CNTRL_LOG("Received DRV_DISCONNECT signal\n");



		/*

		 * if link suspended bring it out of suspend and disable runtime
@@ -187,7 +189,7 @@ static void mhi_arch_pci_link_state_cb(struct msm_pcie_notify *notify) 
		pm_runtime_forbid(&pci_dev->dev);

		break;

	default:

		MHI_ERR("Unhandled event 0x%x\n", notify->event);

		MHI_CNTRL_LOG("Unhandled event 0x%x\n", notify->event);

	}

}
@@ -200,12 +202,12 @@ static int mhi_arch_esoc_ops_power_on(void *priv, unsigned int flags) 


	mutex_lock(&mhi_cntrl->pm_mutex);

	if (mhi_dev->powered_on) {

		MHI_LOG("MHI still in active state\n");

		MHI_CNTRL_LOG("MHI still in active state\n");

		mutex_unlock(&mhi_cntrl->pm_mutex);

		return 0;

	}



	MHI_LOG("Enter: mdm_crashed:%d\n", flags & ESOC_HOOK_MDM_CRASH);

	MHI_CNTRL_LOG("Enter: mdm_crashed:%d\n", flags & ESOC_HOOK_MDM_CRASH);



	/* reset rpm state */

	pm_runtime_set_active(&pci_dev->dev);
@@ -214,7 +216,7 @@ static int mhi_arch_esoc_ops_power_on(void *priv, unsigned int flags) 
	pm_runtime_forbid(&pci_dev->dev);

	ret = pm_runtime_get_sync(&pci_dev->dev);

	if (ret < 0) {

		MHI_ERR("Error with rpm resume, ret:%d\n", ret);

		MHI_CNTRL_ERR("Error with rpm resume, ret:%d\n", ret);

		return ret;

	}
@@ -222,7 +224,7 @@ static int mhi_arch_esoc_ops_power_on(void *priv, unsigned int flags) 
	ret = msm_pcie_pm_control(MSM_PCIE_RESUME, pci_dev->bus->number,

				  pci_dev, NULL, 0);

	if (ret) {

		MHI_ERR("Failed to resume pcie bus ret %d\n", ret);

		MHI_CNTRL_ERR("Failed to resume pcie bus ret %d\n", ret);

		return ret;

	}
@@ -234,7 +236,7 @@ static void mhi_arch_link_off(struct mhi_controller *mhi_cntrl) 
	struct mhi_dev *mhi_dev = mhi_controller_get_devdata(mhi_cntrl);

	struct pci_dev *pci_dev = mhi_dev->pci_dev;



	MHI_LOG("Entered\n");

	MHI_CNTRL_LOG("Entered\n");



	pci_set_power_state(pci_dev, PCI_D3hot);
@@ -242,7 +244,7 @@ static void mhi_arch_link_off(struct mhi_controller *mhi_cntrl) 
	msm_pcie_pm_control(MSM_PCIE_SUSPEND, mhi_cntrl->bus, pci_dev, NULL, 0);

	mhi_arch_set_bus_request(mhi_cntrl, 0);



	MHI_LOG("Exited\n");

	MHI_CNTRL_LOG("Exited\n");

}



static void mhi_arch_esoc_ops_power_off(void *priv, unsigned int flags)
@@ -253,7 +255,7 @@ static void mhi_arch_esoc_ops_power_off(void *priv, unsigned int flags) 
	struct pci_dev *pci_dev = mhi_dev->pci_dev;

	bool mdm_state = (flags & ESOC_HOOK_MDM_CRASH);



	MHI_LOG("Enter: mdm_crashed:%d\n", mdm_state);

	MHI_CNTRL_LOG("Enter: mdm_crashed:%d\n", mdm_state);



	/*

	 * Abort system suspend if system is preparing to go to suspend
@@ -269,7 +271,7 @@ static void mhi_arch_esoc_ops_power_off(void *priv, unsigned int flags) 


	mutex_lock(&mhi_cntrl->pm_mutex);

	if (!mhi_dev->powered_on) {

		MHI_LOG("Not in active state\n");

		MHI_CNTRL_LOG("Not in active state\n");

		mutex_unlock(&mhi_cntrl->pm_mutex);

		pm_runtime_put_noidle(&pci_dev->dev);

		return;
@@ -279,7 +281,7 @@ static void mhi_arch_esoc_ops_power_off(void *priv, unsigned int flags) 


	pm_runtime_put_noidle(&pci_dev->dev);



	MHI_LOG("Triggering shutdown process\n");

	MHI_CNTRL_LOG("Triggering shutdown process\n");

	mhi_power_down(mhi_cntrl, !mdm_state);



	/* turn the link off */
@@ -296,12 +298,10 @@ static void mhi_arch_esoc_ops_mdm_error(void *priv) 
{

	struct mhi_controller *mhi_cntrl = priv;



	MHI_LOG("Enter: mdm asserted\n");

	MHI_CNTRL_LOG("Enter: mdm asserted\n");



	/* transition MHI state into error state */

	mhi_control_error(mhi_cntrl);



	MHI_LOG("Exit\n");

}



static void mhi_bl_dl_cb(struct mhi_device *mhi_device,
@@ -378,8 +378,9 @@ static int mhi_arch_pcie_scale_bw(struct mhi_controller *mhi_cntrl, 
	/* do a bus scale vote based on gen speeds */

	mhi_arch_set_bus_request(mhi_cntrl, link_info->target_link_speed);



	MHI_VERB("bw changed to speed:0x%x width:0x%x\n",

		 link_info->target_link_speed, link_info->target_link_width);

	MHI_LOG("BW changed to speed:0x%x width:0x%x\n",

		link_info->target_link_speed,

		link_info->target_link_width);



	return 0;

}
@@ -406,7 +407,7 @@ static int mhi_bl_probe(struct mhi_device *mhi_device, 
		 mhi_device->slot);



	arch_info->boot_dev = mhi_device;

	arch_info->boot_ipc_log = ipc_log_context_create(MHI_IPC_LOG_PAGES,

	arch_info->boot_ipc_log = ipc_log_context_create(MHI_CNTRL_LOG_PAGES,

							 node_name, 0);

	ipc_log_string(arch_info->boot_ipc_log, HLOG

		       "Entered SBL, Session ID:0x%x\n", mhi_cntrl->session_id);
@@ -461,6 +462,12 @@ int mhi_arch_pcie_init(struct mhi_controller *mhi_cntrl) 
							    node, 0);

		mhi_cntrl->log_lvl = mhi_ipc_log_lvl;



		snprintf(node, sizeof(node), "mhi_cntrl_%04x_%02u.%02u.%02u",

			 mhi_cntrl->dev_id, mhi_cntrl->domain, mhi_cntrl->bus,

			 mhi_cntrl->slot);

		mhi_cntrl->cntrl_log_buf = ipc_log_context_create(

						MHI_CNTRL_LOG_PAGES, node, 0);



		snprintf(node, sizeof(node), "mhi_tsync_%04x_%02u.%02u.%02u",

			 mhi_cntrl->dev_id, mhi_cntrl->domain, mhi_cntrl->bus,

			 mhi_cntrl->slot);
@@ -516,7 +523,8 @@ int mhi_arch_pcie_init(struct mhi_controller *mhi_cntrl) 
		reg_event->notify.data = mhi_cntrl;

		ret = msm_pcie_register_event(reg_event);

		if (ret)

			MHI_LOG("Failed to reg. for link up notification\n");

			MHI_CNTRL_ERR(

				"Failed to reg. for link up notification\n");



		init_completion(&arch_info->pm_completion);
@@ -533,7 +541,7 @@ int mhi_arch_pcie_init(struct mhi_controller *mhi_cntrl) 
		arch_info->esoc_client = devm_register_esoc_client(

						&mhi_dev->pci_dev->dev, "mdm");

		if (IS_ERR_OR_NULL(arch_info->esoc_client)) {

			MHI_ERR("Failed to register esoc client\n");

			MHI_CNTRL_ERR("Failed to register esoc client\n");

		} else {

			/* register for power on/off hooks */

			struct esoc_client_hook *esoc_ops =
@@ -551,7 +559,7 @@ int mhi_arch_pcie_init(struct mhi_controller *mhi_cntrl) 
			ret = esoc_register_client_hook(arch_info->esoc_client,

							esoc_ops);

			if (ret)

				MHI_ERR("Failed to register esoc ops\n");

				MHI_CNTRL_ERR("Failed to register esoc ops\n");

		}



		/*
@@ -602,7 +610,7 @@ static int mhi_arch_drv_suspend(struct mhi_controller *mhi_cntrl) 
		link_info.target_link_width = cur_link_info->target_link_width;

		ret = mhi_arch_pcie_scale_bw(mhi_cntrl, pci_dev, &link_info);

		if (ret) {

			MHI_ERR("Failed to switch Gen1 speed\n");

			MHI_CNTRL_ERR("Failed to switch Gen1 speed\n");

			return -EBUSY;

		}
@@ -632,7 +640,8 @@ int mhi_arch_link_suspend(struct mhi_controller *mhi_cntrl) 
	struct pci_dev *pci_dev = mhi_dev->pci_dev;

	int ret = 0;



	MHI_LOG("Entered\n");

	MHI_LOG("Entered with suspend_mode:%s\n",

		TO_MHI_SUSPEND_MODE_STR(mhi_dev->suspend_mode));



	/* disable inactivity timer */

	msm_pcie_l1ss_timeout_disable(pci_dev);
@@ -642,7 +651,8 @@ int mhi_arch_link_suspend(struct mhi_controller *mhi_cntrl) 
		pci_clear_master(pci_dev);

		ret = pci_save_state(mhi_dev->pci_dev);

		if (ret) {

			MHI_ERR("Failed with pci_save_state, ret:%d\n", ret);

			MHI_CNTRL_ERR("Failed with pci_save_state, ret:%d\n",

				      ret);

			goto exit_suspend;

		}
@@ -661,6 +671,7 @@ int mhi_arch_link_suspend(struct mhi_controller *mhi_cntrl) 
		break;

	case MHI_ACTIVE_STATE:

	case MHI_FAST_LINK_ON:/* keeping link on do nothing */

	default:

		break;

	}
@@ -681,8 +692,6 @@ static int __mhi_arch_link_resume(struct mhi_controller *mhi_cntrl) 
	struct mhi_link_info *cur_info = &mhi_cntrl->mhi_link_info;

	int ret;



	MHI_LOG("Entered\n");



	/* request bus scale voting based on higher gen speed */

	ret = mhi_arch_set_bus_request(mhi_cntrl,

				       cur_info->target_link_speed);
@@ -725,7 +734,8 @@ int mhi_arch_link_resume(struct mhi_controller *mhi_cntrl) 
	struct mhi_link_info *cur_info = &mhi_cntrl->mhi_link_info;

	int ret = 0;



	MHI_LOG("Entered\n");

	MHI_LOG("Entered with suspend_mode:%s\n",

		TO_MHI_SUSPEND_MODE_STR(mhi_dev->suspend_mode));



	switch (mhi_dev->suspend_mode) {

	case MHI_DEFAULT_SUSPEND:
@@ -743,26 +753,23 @@ int mhi_arch_link_resume(struct mhi_controller *mhi_cntrl) 
		 * only print an error here.

		 */

		if (mhi_arch_pcie_scale_bw(mhi_cntrl, pci_dev, cur_info))

			MHI_ERR(

			MHI_CNTRL_ERR(

			"Failed to honor bw request: speed:0x%x width:0x%x\n",

			cur_info->target_link_speed,

			cur_info->target_link_width);

		break;

	case MHI_ACTIVE_STATE:

	case MHI_FAST_LINK_ON:

	default:

		break;

	}



	if (ret) {

		MHI_ERR("Link training failed, ret:%d\n", ret);

		return ret;

	}



	if (!ret)

		msm_pcie_l1ss_timeout_enable(pci_dev);



	MHI_LOG("Exited\n");

	MHI_LOG("Exited with ret:%d\n", ret);



	return 0;

	return ret;

}



int mhi_arch_link_lpm_disable(struct mhi_controller *mhi_cntrl)

drivers/bus/mhi/controllers/mhi_qcom.c

+21 −14
Original line number Diff line number Diff line
@@ -33,12 +33,19 @@ static const struct firmware_info firmware_table[] = { 


static int debug_mode;



const char * const mhi_suspend_mode_str[MHI_SUSPEND_MODE_MAX] = {

	[MHI_ACTIVE_STATE] = "Active",

	[MHI_DEFAULT_SUSPEND] = "Default",

	[MHI_FAST_LINK_OFF] = "Fast Link Off",

	[MHI_FAST_LINK_ON] = "Fast Link On",

};



int mhi_debugfs_trigger_m0(void *data, u64 val)

{

	struct mhi_controller *mhi_cntrl = data;

	struct mhi_dev *mhi_dev = mhi_controller_get_devdata(mhi_cntrl);



	MHI_LOG("Trigger M3 Exit\n");

	MHI_CNTRL_LOG("Trigger M3 Exit\n");

	pm_runtime_get(&mhi_dev->pci_dev->dev);

	pm_runtime_put(&mhi_dev->pci_dev->dev);
@@ -52,7 +59,7 @@ int mhi_debugfs_trigger_m3(void *data, u64 val) 
	struct mhi_controller *mhi_cntrl = data;

	struct mhi_dev *mhi_dev = mhi_controller_get_devdata(mhi_cntrl);



	MHI_LOG("Trigger M3 Entry\n");

	MHI_CNTRL_LOG("Trigger M3 Entry\n");

	pm_runtime_mark_last_busy(&mhi_dev->pci_dev->dev);

	pm_request_autosuspend(&mhi_dev->pci_dev->dev);
@@ -91,19 +98,19 @@ static int mhi_init_pci_dev(struct mhi_controller *mhi_cntrl) 
	mhi_dev->resn = MHI_PCI_BAR_NUM;

	ret = pci_assign_resource(pci_dev, mhi_dev->resn);

	if (ret) {

		MHI_ERR("Error assign pci resources, ret:%d\n", ret);

		MHI_CNTRL_ERR("Error assign pci resources, ret:%d\n", ret);

		return ret;

	}



	ret = pci_enable_device(pci_dev);

	if (ret) {

		MHI_ERR("Error enabling device, ret:%d\n", ret);

		MHI_CNTRL_ERR("Error enabling device, ret:%d\n", ret);

		goto error_enable_device;

	}



	ret = pci_request_region(pci_dev, mhi_dev->resn, "mhi");

	if (ret) {

		MHI_ERR("Error pci_request_region, ret:%d\n", ret);

		MHI_CNTRL_ERR("Error pci_request_region, ret:%d\n", ret);

		goto error_request_region;

	}
@@ -113,14 +120,14 @@ static int mhi_init_pci_dev(struct mhi_controller *mhi_cntrl) 
	len = pci_resource_len(pci_dev, mhi_dev->resn);

	mhi_cntrl->regs = ioremap_nocache(mhi_cntrl->base_addr, len);

	if (!mhi_cntrl->regs) {

		MHI_ERR("Error ioremap region\n");

		MHI_CNTRL_ERR("Error ioremap region\n");

		goto error_ioremap;

	}



	ret = pci_alloc_irq_vectors(pci_dev, mhi_cntrl->msi_required,

				    mhi_cntrl->msi_required, PCI_IRQ_MSI);

	if (IS_ERR_VALUE((ulong)ret) || ret < mhi_cntrl->msi_required) {

		MHI_ERR("Failed to enable MSI, ret:%d\n", ret);

		MHI_CNTRL_ERR("Failed to enable MSI, ret:%d\n", ret);

		goto error_req_msi;

	}
@@ -394,7 +401,7 @@ static int mhi_force_suspend(struct mhi_controller *mhi_cntrl) 
	struct mhi_dev *mhi_dev = mhi_controller_get_devdata(mhi_cntrl);

	int itr = DIV_ROUND_UP(mhi_cntrl->timeout_ms, delayms);



	MHI_LOG("Entered\n");

	MHI_CNTRL_LOG("Entered\n");



	mutex_lock(&mhi_cntrl->pm_mutex);
@@ -410,12 +417,12 @@ static int mhi_force_suspend(struct mhi_controller *mhi_cntrl) 
		if (!ret || ret != -EBUSY)

			break;



		MHI_LOG("MHI busy, sleeping and retry\n");

		MHI_CNTRL_LOG("MHI busy, sleeping and retry\n");

		msleep(delayms);

	}



	if (ret) {

		MHI_ERR("Force suspend ret with %d\n", ret);

		MHI_CNTRL_ERR("Force suspend ret:%d\n", ret);

		goto exit_force_suspend;

	}
@@ -551,14 +558,14 @@ static void mhi_status_cb(struct mhi_controller *mhi_cntrl, 
		pm_runtime_get(dev);

		ret = mhi_force_suspend(mhi_cntrl);

		if (!ret) {

			MHI_LOG("Attempt resume after forced suspend\n");

			MHI_CNTRL_LOG("Attempt resume after forced suspend\n");

			mhi_runtime_resume(dev);

		}

		pm_runtime_put(dev);

		mhi_arch_mission_mode_enter(mhi_cntrl);

		break;

	default:

		MHI_ERR("Unhandled cb:0x%x\n", reason);

		MHI_CNTRL_LOG("Unhandled cb:0x%x\n", reason);

	}

}
@@ -772,7 +779,7 @@ static struct mhi_controller *mhi_register_controller(struct pci_dev *pci_dev) 
	atomic_set(&mhi_cntrl->write_idx, -1);



	if (sysfs_create_group(&mhi_cntrl->mhi_dev->dev.kobj, &mhi_qcom_group))

		MHI_ERR("Error while creating the sysfs group\n");

		MHI_CNTRL_ERR("Error while creating the sysfs group\n");



	return mhi_cntrl;
@@ -829,7 +836,7 @@ int mhi_pci_probe(struct pci_dev *pci_dev, 


	pm_runtime_mark_last_busy(&pci_dev->dev);



	MHI_LOG("Return successful\n");

	MHI_CNTRL_LOG("Return successful\n");



	return 0;

drivers/bus/mhi/controllers/mhi_qcom.h

+4 −1
Original line number Diff line number Diff line
@@ -38,9 +38,12 @@ enum mhi_suspend_mode { 
	MHI_DEFAULT_SUSPEND,

	MHI_FAST_LINK_OFF,

	MHI_FAST_LINK_ON,

	MHI_SUSPEND_MODE_MAX,

};



#define MHI_IS_SUSPENDED(mode) (mode)

extern const char * const mhi_suspend_mode_str[MHI_SUSPEND_MODE_MAX];

#define TO_MHI_SUSPEND_MODE_STR(mode) \

	(mode >= MHI_SUSPEND_MODE_MAX ? "Invalid" : mhi_suspend_mode_str[mode])



struct mhi_dev {

	struct pci_dev *pci_dev;

drivers/bus/mhi/core/mhi_boot.c

+54 −53
Original line number Diff line number Diff line
@@ -51,7 +51,7 @@ static void mhi_process_sfr(struct mhi_controller *mhi_cntrl, 
		rem_seg_len = 0;

		seg_idx++;

		if (seg_idx == mhi_cntrl->rddm_image->entries) {

			MHI_ERR("invalid size for SFR file\n");

			MHI_CNTRL_ERR("invalid size for SFR file\n");

			goto err;

		}

	}
@@ -80,7 +80,7 @@ static int mhi_find_next_file_offset(struct mhi_controller *mhi_cntrl, 
	while (info->file_size) {

		info->seg_idx++;

		if (info->seg_idx == mhi_cntrl->rddm_image->entries) {

			MHI_ERR("invalid size for file %s\n",

			MHI_CNTRL_ERR("invalid size for file %s\n",

					table_info->file_name);

			return -EINVAL;

		}
@@ -111,14 +111,14 @@ void mhi_dump_sfr(struct mhi_controller *mhi_cntrl) 


	if (rddm_header->header_size > sizeof(*rddm_header) ||

			rddm_header->header_size < 8) {

		MHI_ERR("invalid reported header size %u\n",

		MHI_CNTRL_ERR("invalid reported header size %u\n",

				rddm_header->header_size);

		return;

	}



	table_size = (rddm_header->header_size - 8) / sizeof(*table_info);

	if (!table_size) {

		MHI_ERR("invalid rddm table size %u\n", table_size);

		MHI_CNTRL_ERR("invalid rddm table size %u\n", table_size);

		return;

	}
@@ -150,13 +150,13 @@ void mhi_rddm_prepare(struct mhi_controller *mhi_cntrl, 
	int i = 0;



	for (i = 0; i < img_info->entries - 1; i++, mhi_buf++, bhi_vec++) {

		MHI_VERB("Setting vector:%pad size:%zu\n",

		MHI_CNTRL_LOG("Setting vector:%pad size:%zu\n",

				&mhi_buf->dma_addr, mhi_buf->len);

		bhi_vec->dma_addr = mhi_buf->dma_addr;

		bhi_vec->size = mhi_buf->len;

	}



	MHI_LOG("BHIe programming for RDDM\n");

	MHI_CNTRL_LOG("BHIe programming for RDDM\n");



	mhi_cntrl->write_reg(mhi_cntrl, base, BHIE_RXVECADDR_HIGH_OFFS,

		      upper_32_bits(mhi_buf->dma_addr));
@@ -175,7 +175,7 @@ void mhi_rddm_prepare(struct mhi_controller *mhi_cntrl, 
			    BHIE_RXVECDB_SEQNUM_BMSK, BHIE_RXVECDB_SEQNUM_SHFT,

			    sequence_id);



	MHI_LOG("address:%pad len:0x%lx sequence:%u\n",

	MHI_CNTRL_LOG("address:%pad len:0x%lx sequence:%u\n",

			&mhi_buf->dma_addr, mhi_buf->len, sequence_id);

}
@@ -191,7 +191,7 @@ static int __mhi_download_rddm_in_panic(struct mhi_controller *mhi_cntrl) 
	int rddm_retry = rddm_timeout_us / delayus; /* time to enter rddm */

	void __iomem *base = mhi_cntrl->bhie;



	MHI_LOG("Entered with pm_state:%s dev_state:%s ee:%s\n",

	MHI_CNTRL_LOG("Entered with pm_state:%s dev_state:%s ee:%s\n",

			to_mhi_pm_state_str(mhi_cntrl->pm_state),

			TO_MHI_STATE_STR(mhi_cntrl->dev_state),

			TO_MHI_EXEC_STR(mhi_cntrl->ee));
@@ -219,10 +219,10 @@ static int __mhi_download_rddm_in_panic(struct mhi_controller *mhi_cntrl) 
	ee = mhi_get_exec_env(mhi_cntrl);

	if (ee != MHI_EE_RDDM) {



		MHI_LOG("Trigger device into RDDM mode using SYSERR\n");

		MHI_CNTRL_LOG("Trigger device into RDDM mode using SYSERR\n");

		mhi_set_mhi_state(mhi_cntrl, MHI_STATE_SYS_ERR);



		MHI_LOG("Waiting for device to enter RDDM\n");

		MHI_CNTRL_LOG("Waiting for device to enter RDDM\n");

		while (rddm_retry--) {

			ee = mhi_get_exec_env(mhi_cntrl);

			if (ee == MHI_EE_RDDM)
@@ -233,7 +233,7 @@ static int __mhi_download_rddm_in_panic(struct mhi_controller *mhi_cntrl) 


		if (rddm_retry <= 0) {

			/* Hardware reset; force device to enter rddm */

			MHI_LOG(

			MHI_CNTRL_LOG(

				"Did not enter RDDM, do a host req. reset\n");

			mhi_cntrl->write_reg(mhi_cntrl, mhi_cntrl->regs,

				      MHI_SOC_RESET_REQ_OFFSET,
@@ -244,7 +244,7 @@ static int __mhi_download_rddm_in_panic(struct mhi_controller *mhi_cntrl) 
		ee = mhi_get_exec_env(mhi_cntrl);

	}



	MHI_LOG("Waiting for image download completion, current EE:%s\n",

	MHI_CNTRL_LOG("Waiting for image download completion, current EE:%s\n",

			TO_MHI_EXEC_STR(ee));

	while (retry--) {

		ret = mhi_read_reg_field(mhi_cntrl, base, BHIE_RXVECSTATUS_OFFS,
@@ -255,7 +255,7 @@ static int __mhi_download_rddm_in_panic(struct mhi_controller *mhi_cntrl) 
			return -EIO;



		if (rx_status == BHIE_RXVECSTATUS_STATUS_XFER_COMPL) {

			MHI_LOG("RDDM successfully collected\n");

			MHI_CNTRL_LOG("RDDM successfully collected\n");

			return 0;

		}
@@ -265,9 +265,9 @@ static int __mhi_download_rddm_in_panic(struct mhi_controller *mhi_cntrl) 
	ee = mhi_get_exec_env(mhi_cntrl);

	ret = mhi_read_reg(mhi_cntrl, base, BHIE_RXVECSTATUS_OFFS, &rx_status);



	MHI_ERR("Did not complete RDDM transfer\n");

	MHI_ERR("Current EE:%s\n", TO_MHI_EXEC_STR(ee));

	MHI_ERR("RXVEC_STATUS:0x%x, ret:%d\n", rx_status, ret);

	MHI_CNTRL_ERR("Did not complete RDDM transfer\n");

	MHI_CNTRL_ERR("Current EE:%s\n", TO_MHI_EXEC_STR(ee));

	MHI_CNTRL_ERR("RXVEC_STATUS:0x%x, ret:%d\n", rx_status, ret);



	return -EIO;

}
@@ -281,7 +281,7 @@ int mhi_download_rddm_img(struct mhi_controller *mhi_cntrl, bool in_panic) 
	if (in_panic)

		return __mhi_download_rddm_in_panic(mhi_cntrl);



	MHI_LOG("Waiting for image download completion\n");

	MHI_CNTRL_LOG("Waiting for image download completion\n");



	/* waiting for image download completion */

	wait_event_timeout(mhi_cntrl->state_event,
@@ -309,7 +309,7 @@ static int mhi_fw_load_amss(struct mhi_controller *mhi_cntrl, 
		return -EIO;

	}



	MHI_LOG("Starting BHIe Programming\n");

	MHI_CNTRL_LOG("Starting BHIe Programming\n");



	mhi_cntrl->write_reg(mhi_cntrl, base, BHIE_TXVECADDR_HIGH_OFFS,

		      upper_32_bits(mhi_buf->dma_addr));
@@ -329,11 +329,11 @@ static int mhi_fw_load_amss(struct mhi_controller *mhi_cntrl, 
			    mhi_cntrl->sequence_id);

	read_unlock_bh(pm_lock);



	MHI_LOG("Upper:0x%x Lower:0x%x len:0x%lx sequence:%u\n",

	MHI_CNTRL_LOG("Upper:0x%x Lower:0x%x len:0x%lx sequence:%u\n",

			upper_32_bits(mhi_buf->dma_addr),

			lower_32_bits(mhi_buf->dma_addr),

			mhi_buf->len, mhi_cntrl->sequence_id);

	MHI_LOG("Waiting for image transfer completion\n");

	MHI_CNTRL_LOG("Waiting for image transfer completion\n");



	/* waiting for image download completion */

	wait_event_timeout(mhi_cntrl->state_event,
@@ -370,7 +370,7 @@ static int mhi_fw_load_sbl(struct mhi_controller *mhi_cntrl, 
		{ NULL },

	};



	MHI_LOG("Starting BHI programming\n");

	MHI_CNTRL_LOG("Starting BHI programming\n");



	/* program start sbl download via  bhi protocol */

	read_lock_bh(pm_lock);
@@ -393,7 +393,7 @@ static int mhi_fw_load_sbl(struct mhi_controller *mhi_cntrl, 
			mhi_cntrl->session_id);

	read_unlock_bh(pm_lock);



	MHI_LOG("Waiting for image transfer completion\n");

	MHI_CNTRL_LOG("Waiting for image transfer completion\n");



	/* waiting for image download completion */

	wait_event_timeout(mhi_cntrl->state_event,
@@ -406,7 +406,7 @@ static int mhi_fw_load_sbl(struct mhi_controller *mhi_cntrl, 
		goto invalid_pm_state;



	if (tx_status == BHI_STATUS_ERROR) {

		MHI_ERR("Image transfer failed\n");

		MHI_CNTRL_ERR("Image transfer failed\n");

		read_lock_bh(pm_lock);

		if (MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state)) {

			for (i = 0; error_reg[i].name; i++) {
@@ -414,7 +414,7 @@ static int mhi_fw_load_sbl(struct mhi_controller *mhi_cntrl, 
						   error_reg[i].offset, &val);

				if (ret)

					break;

				MHI_ERR("reg:%s value:0x%x\n",

				MHI_CNTRL_ERR("reg:%s value:0x%x\n",

					      error_reg[i].name, val);

			}

		}
@@ -454,7 +454,7 @@ int mhi_alloc_bhie_table(struct mhi_controller *mhi_cntrl, 
	struct image_info *img_info;

	struct mhi_buf *mhi_buf;



	MHI_LOG("Allocating bytes:%zu seg_size:%zu total_seg:%u\n",

	MHI_CNTRL_LOG("Allocating bytes:%zu seg_size:%zu total_seg:%u\n",

			alloc_size, seg_size, segments);



	img_info = kzalloc(sizeof(*img_info), GFP_KERNEL);
@@ -482,7 +482,7 @@ int mhi_alloc_bhie_table(struct mhi_controller *mhi_cntrl, 
		if (!mhi_buf->buf)

			goto error_alloc_segment;



		MHI_LOG("Entry:%d Address:0x%llx size:%lu\n", i,

		MHI_CNTRL_LOG("Entry:%d Address:0x%llx size:%lu\n", i,

			mhi_buf->dma_addr, mhi_buf->len);

	}
@@ -490,7 +490,7 @@ int mhi_alloc_bhie_table(struct mhi_controller *mhi_cntrl, 
	img_info->entries = segments;

	*image_info = img_info;



	MHI_LOG("Successfully allocated bhi vec table\n");

	MHI_CNTRL_LOG("Successfully allocated bhi vec table\n");



	return 0;
@@ -545,11 +545,11 @@ void mhi_fw_load_handler(struct mhi_controller *mhi_cntrl) 
	size_t size;



	if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {

		MHI_ERR("MHI is not in valid state\n");

		MHI_CNTRL_ERR("MHI is not in valid state\n");

		return;

	}



	MHI_LOG("Device current EE:%s\n", TO_MHI_EXEC_STR(mhi_cntrl->ee));

	MHI_CNTRL_LOG("Device current EE:%s\n", TO_MHI_EXEC_STR(mhi_cntrl->ee));



	/* if device in pthru, do reset to ready state transition */

	if (mhi_cntrl->ee == MHI_EE_PTHRU)
@@ -560,14 +560,15 @@ void mhi_fw_load_handler(struct mhi_controller *mhi_cntrl) 


	if (!fw_name || (mhi_cntrl->fbc_download && (!mhi_cntrl->sbl_size ||

						     !mhi_cntrl->seg_len))) {

		MHI_ERR("No firmware image defined or !sbl_size || !seg_len\n");

		MHI_CNTRL_ERR(

			"No firmware image defined or !sbl_size || !seg_len\n");

		return;

	}



	ret = request_firmware(&firmware, fw_name, mhi_cntrl->dev);

	if (ret) {

		if (!mhi_cntrl->fw_image_fallback) {

			MHI_ERR("Error loading fw, ret:%d\n", ret);

			MHI_CNTRL_ERR("Error loading fw, ret:%d\n", ret);

			return;

		}
@@ -575,7 +576,7 @@ void mhi_fw_load_handler(struct mhi_controller *mhi_cntrl) 
		ret = request_firmware(&firmware, mhi_cntrl->fw_image_fallback,

				mhi_cntrl->dev);

		if (ret) {

			MHI_ERR("Error loading fw_fb, ret:%d\n", ret);

			MHI_CNTRL_ERR("Error loading fw_fb, ret:%d\n", ret);

			return;

		}
@@ -591,7 +592,7 @@ void mhi_fw_load_handler(struct mhi_controller *mhi_cntrl) 


	buf = mhi_alloc_coherent(mhi_cntrl, size, &dma_addr, GFP_KERNEL);

	if (!buf) {

		MHI_ERR("Could not allocate memory for image\n");

		MHI_CNTRL_ERR("Could not allocate memory for image\n");

		release_firmware(firmware);

		return;

	}
@@ -620,11 +621,11 @@ void mhi_fw_load_handler(struct mhi_controller *mhi_cntrl) 
		ret = mhi_alloc_bhie_table(mhi_cntrl, &mhi_cntrl->fbc_image,

					   firmware->size);

		if (ret) {

			MHI_ERR("Error alloc size of %zu\n", firmware->size);

			MHI_CNTRL_ERR("Error alloc size:%zu\n", firmware->size);

			goto error_alloc_fw_table;

		}



		MHI_LOG("Copying firmware image into vector table\n");

		MHI_CNTRL_LOG("Copying firmware image into vector table\n");



		/* load the firmware into BHIE vec table */

		mhi_firmware_copy(mhi_cntrl, firmware, mhi_cntrl->fbc_image);
@@ -634,7 +635,7 @@ void mhi_fw_load_handler(struct mhi_controller *mhi_cntrl) 
	/* transitioning into MHI RESET->READY state */

	ret = mhi_ready_state_transition(mhi_cntrl);



	MHI_LOG("To Reset->Ready PM_STATE:%s MHI_STATE:%s EE:%s, ret:%d\n",

	MHI_CNTRL_LOG("To Reset->Ready PM_STATE:%s MHI_STATE:%s EE:%s ret:%d\n",

			to_mhi_pm_state_str(mhi_cntrl->pm_state),

			TO_MHI_STATE_STR(mhi_cntrl->dev_state),

			TO_MHI_EXEC_STR(mhi_cntrl->ee), ret);
@@ -643,7 +644,7 @@ void mhi_fw_load_handler(struct mhi_controller *mhi_cntrl) 
		return;



	if (ret) {

		MHI_ERR("Did not transition to READY state\n");

		MHI_CNTRL_ERR("Did not transition to READY state\n");

		goto error_read;

	}
@@ -654,7 +655,7 @@ void mhi_fw_load_handler(struct mhi_controller *mhi_cntrl) 
				 msecs_to_jiffies(mhi_cntrl->timeout_ms));



	if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {

		MHI_ERR("MHI did not enter BHIE\n");

		MHI_CNTRL_ERR("MHI did not enter BHIE\n");

		goto error_read;

	}
@@ -664,7 +665,7 @@ void mhi_fw_load_handler(struct mhi_controller *mhi_cntrl) 
			       /* last entry is vec table */

			       &image_info->mhi_buf[image_info->entries - 1]);



	MHI_LOG("amss fw_load, ret:%d\n", ret);

	MHI_CNTRL_LOG("amss fw_load ret:%d\n", ret);



	release_firmware(firmware);

drivers/bus/mhi/core/mhi_init.c

+15 −15
Original line number Diff line number Diff line
@@ -435,7 +435,7 @@ int mhi_init_irq_setup(struct mhi_controller *mhi_cntrl) 
				  mhi_msi_handlr, IRQF_SHARED | IRQF_NO_SUSPEND,

				  "mhi", mhi_event);

		if (ret) {

			MHI_ERR("Error requesting irq:%d for ev:%d\n",

			MHI_CNTRL_ERR("Error requesting irq:%d for ev:%d\n",

					mhi_cntrl->irq[mhi_event->msi], i);

			goto error_request;

		}
@@ -792,7 +792,7 @@ static int mhi_init_timesync(struct mhi_controller *mhi_cntrl) 
	ret = mhi_get_capability_offset(mhi_cntrl, TIMESYNC_CAP_ID,

					&time_offset);

	if (ret) {

		MHI_LOG("No timesync capability found\n");

		MHI_CNTRL_LOG("No timesync capability found\n");

		return ret;

	}
@@ -807,7 +807,7 @@ static int mhi_init_timesync(struct mhi_controller *mhi_cntrl) 
	INIT_LIST_HEAD(&mhi_tsync->head);



	/* save time_offset for obtaining time */

	MHI_LOG("TIME OFFS:0x%x\n", time_offset);

	MHI_CNTRL_LOG("TIME OFFS:0x%x\n", time_offset);

	mhi_tsync->time_reg = mhi_cntrl->regs + time_offset

			      + TIMESYNC_TIME_LOW_OFFSET;
@@ -816,7 +816,7 @@ static int mhi_init_timesync(struct mhi_controller *mhi_cntrl) 
	/* get timesync event ring configuration */

	er_index = mhi_get_er_index(mhi_cntrl, MHI_ER_TSYNC_ELEMENT_TYPE);

	if (er_index < 0) {

		MHI_LOG("Could not find timesync event ring\n");

		MHI_CNTRL_LOG("Could not find timesync event ring\n");

		return er_index;

	}
@@ -845,7 +845,7 @@ int mhi_init_sfr(struct mhi_controller *mhi_cntrl) 
	sfr_info->buf_addr = mhi_alloc_coherent(mhi_cntrl, sfr_info->len,

					&sfr_info->dma_addr, GFP_KERNEL);

	if (!sfr_info->buf_addr) {

		MHI_ERR("Failed to allocate memory for sfr\n");

		MHI_CNTRL_ERR("Failed to allocate memory for sfr\n");

		return -ENOMEM;

	}
@@ -853,14 +853,14 @@ int mhi_init_sfr(struct mhi_controller *mhi_cntrl) 


	ret = mhi_send_cmd(mhi_cntrl, NULL, MHI_CMD_SFR_CFG);

	if (ret) {

		MHI_ERR("Failed to send sfr cfg cmd\n");

		MHI_CNTRL_ERR("Failed to send sfr cfg cmd\n");

		return ret;

	}



	ret = wait_for_completion_timeout(&sfr_info->completion,

			msecs_to_jiffies(mhi_cntrl->timeout_ms));

	if (!ret || sfr_info->ccs != MHI_EV_CC_SUCCESS) {

		MHI_ERR("Failed to get sfr cfg cmd completion\n");

		MHI_CNTRL_ERR("Failed to get sfr cfg cmd completion\n");

		return -EIO;

	}
@@ -888,7 +888,7 @@ static int mhi_init_bw_scale(struct mhi_controller *mhi_cntrl) 


	bw_cfg_offset += BW_SCALE_CFG_OFFSET;



	MHI_LOG("BW_CFG OFFSET:0x%x\n", bw_cfg_offset);

	MHI_CNTRL_LOG("BW_CFG OFFSET:0x%x\n", bw_cfg_offset);



	/* advertise host support */

	mhi_cntrl->write_reg(mhi_cntrl, mhi_cntrl->regs, bw_cfg_offset,
@@ -977,7 +977,7 @@ int mhi_init_mmio(struct mhi_controller *mhi_cntrl) 
		{ 0, 0, 0 }

	};



	MHI_LOG("Initializing MMIO\n");

	MHI_CNTRL_LOG("Initializing MMIO\n");



	/* set up DB register for all the chan rings */

	ret = mhi_read_reg_field(mhi_cntrl, base, CHDBOFF, CHDBOFF_CHDBOFF_MASK,
@@ -985,7 +985,7 @@ int mhi_init_mmio(struct mhi_controller *mhi_cntrl) 
	if (ret)

		return -EIO;



	MHI_LOG("CHDBOFF:0x%x\n", val);

	MHI_CNTRL_LOG("CHDBOFF:0x%x\n", val);



	/* setup wake db */

	mhi_cntrl->wake_db = base + val + (8 * MHI_DEV_WAKE_DB);
@@ -1008,7 +1008,7 @@ int mhi_init_mmio(struct mhi_controller *mhi_cntrl) 
	if (ret)

		return -EIO;



	MHI_LOG("ERDBOFF:0x%x\n", val);

	MHI_CNTRL_LOG("ERDBOFF:0x%x\n", val);



	mhi_event = mhi_cntrl->mhi_event;

	for (i = 0; i < mhi_cntrl->total_ev_rings; i++, val += 8, mhi_event++) {
@@ -1021,7 +1021,7 @@ int mhi_init_mmio(struct mhi_controller *mhi_cntrl) 
	/* set up DB register for primary CMD rings */

	mhi_cntrl->mhi_cmd[PRIMARY_CMD_RING].ring.db_addr = base + CRDB_LOWER;



	MHI_LOG("Programming all MMIO values.\n");

	MHI_CNTRL_LOG("Programming all MMIO values.\n");

	for (i = 0; reg_info[i].offset; i++)

		mhi_write_reg_field(mhi_cntrl, base, reg_info[i].offset,

				    reg_info[i].mask, reg_info[i].shift,
@@ -1772,7 +1772,7 @@ int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl) 


	ret = mhi_init_dev_ctxt(mhi_cntrl);

	if (ret) {

		MHI_ERR("Error with init dev_ctxt\n");

		MHI_CNTRL_ERR("Error with init dev_ctxt\n");

		goto error_dev_ctxt;

	}
@@ -1792,7 +1792,7 @@ int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl) 
			ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIEOFF,

					   &bhie_off);

			if (ret) {

				MHI_ERR("Error getting bhie offset\n");

				MHI_CNTRL_ERR("Error getting bhie offset\n");

				goto bhie_error;

			}