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Commit c97537f9 authored by Shreyas K K's avatar Shreyas K K
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ARM: dts: msm: Add device node for llcc node on SDMSHRIKE 

Add device node for last level cache controller on
SDMSHRIKE target.

Change-Id: I33ef1895e9228cf897942051eb1f7fd7596d79a1
parent 3f45d6a4

bindings/arm/msm/qcom,llcc.txt

+1 −0
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ Properties: 
	Definition: must be "qcom,sdm845-llcc" or "qcom,lahaina-llcc"

	            or "qcom,shima-llcc" or "qcom,sdxlemur-llcc"

	            or "qcom,yupik-llcc" or "qcom,sm8150-llcc"

		    or "qcom,sdmshrike-llcc"

		    "qcom,llcc-v2" must be appended for V2 hardware.



- reg:

qcom/sdmshrike.dtsi

+7 −0
Original line number Diff line number Diff line
@@ -621,6 +621,13 @@ 
		};

	};



	cache-controller@9200000 {

		compatible = "qcom,sdmshrike-llcc";

		reg = <0x9200000 0x1d0000> , <0x9600000 0x50000>;

		reg-names = "llcc_base", "llcc_broadcast_base";

		cap-based-alloc-and-pwr-collapse;

	};



	qcom,msm-imem@146bf000 {

		compatible = "qcom,msm-imem";

		reg = <0x146bf000 0x1000>;