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Commit c94e4ad2 authored by Russell King's avatar Russell King
Browse files

ARM: document and update UNCACHEABLE_ADDR definitions 



Document the UNCACHEABLE_ADDR definitions for footbridge and SA1100
so that we know where they're located and/or what they're accessing.
Change RiscPC to calculate the UNCACHEABLE_ADDR value from FLUSH_BASE
as that's where we locate that.

UNCACHEABLE_ADDR is used to perform an uncached access (ARMv4
terminology) necessary to force a CPU clock-switch to the memory-
speed clock, as required for entering WFI.

Signed-off-by: default avatarRussell King <rmk+kernel@armlinux.org.uk>
parent 83809b90

arch/arm/mach-footbridge/include/mach/hardware.h

+1 −1
Original line number Diff line number Diff line
@@ -59,7 +59,7 @@ 
#define XBUS_SWITCH_J17_11	((*XBUS_SWITCH) & (1 << 5))

#define XBUS_SWITCH_J17_9	((*XBUS_SWITCH) & (1 << 6))



#define UNCACHEABLE_ADDR	(ARMCSR_BASE + 0x108)

#define UNCACHEABLE_ADDR	(ARMCSR_BASE + 0x108)	/* CSR_ROMBASEMASK */





/* PIC irq control */

arch/arm/mach-rpc/include/mach/hardware.h

+1 −1
Original line number Diff line number Diff line
@@ -40,7 +40,7 @@ 
#define SCREEN_END		0xdfc00000

#define SCREEN_BASE		0xdf800000



#define UNCACHEABLE_ADDR	0xdf010000

#define UNCACHEABLE_ADDR	(FLUSH_BASE + 0x10000)



/*

 * IO Addresses

arch/arm/mach-sa1100/include/mach/hardware.h

+1 −1
Original line number Diff line number Diff line
@@ -13,7 +13,7 @@ 
#define __ASM_ARCH_HARDWARE_H





#define UNCACHEABLE_ADDR	0xfa050000

#define UNCACHEABLE_ADDR	0xfa050000	/* ICIP */





/*