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Commit 83809b90 authored by Russell King's avatar Russell King
Browse files

ARM: sa1100: move StrongARM CPU ID checks to cputype.h 



Move the StrongARM CPU ID checks out of the platform's hardware.h
file into asm/cputype.h

Acked-by: default avatarViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: default avatarRussell King <rmk+kernel@armlinux.org.uk>
parent 10b52a49

arch/arm/include/asm/cputype.h

+21 −0
Original line number Diff line number Diff line
@@ -60,6 +60,7 @@ 
	((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK)



#define ARM_CPU_IMP_ARM			0x41

#define ARM_CPU_IMP_DEC			0x44

#define ARM_CPU_IMP_INTEL		0x69



/* ARM implemented processors */
@@ -76,6 +77,17 @@ 
#define ARM_CPU_PART_CORTEX_A15		0x4100c0f0

#define ARM_CPU_PART_MASK		0xff00fff0



/* DEC implemented cores */

#define ARM_CPU_PART_SA1100		0x4400a110



/* Intel implemented cores */

#define ARM_CPU_PART_SA1110		0x6900b110

#define ARM_CPU_REV_SA1110_A0		0

#define ARM_CPU_REV_SA1110_B0		4

#define ARM_CPU_REV_SA1110_B1		5

#define ARM_CPU_REV_SA1110_B2		6

#define ARM_CPU_REV_SA1110_B4		8



#define ARM_CPU_XSCALE_ARCH_MASK	0xe000

#define ARM_CPU_XSCALE_ARCH_V1		0x2000

#define ARM_CPU_XSCALE_ARCH_V2		0x4000
@@ -173,6 +185,11 @@ static inline unsigned int __attribute_const__ read_cpuid_implementor(void) 
	return (read_cpuid_id() & 0xFF000000) >> 24;

}



static inline unsigned int __attribute_const__ read_cpuid_revision(void)

{

	return read_cpuid_id() & 0x0000000f;

}



/*

 * The CPU part number is meaningless without referring to the CPU

 * implementer: implementers are free to define their own part numbers
@@ -208,6 +225,10 @@ static inline unsigned int __attribute_const__ read_cpuid_mpidr(void) 
	return read_cpuid(CPUID_MPIDR);

}



/* StrongARM-11x0 CPUs */

#define cpu_is_sa1100() (read_cpuid_part() == ARM_CPU_PART_SA1100)

#define cpu_is_sa1110() (read_cpuid_part() == ARM_CPU_PART_SA1110)



/*

 * Intel's XScale3 core supports some v6 features (supersections, L2)

 * but advertises itself as v5 as it does not support the v6 ISA.  For

arch/arm/mach-sa1100/include/mach/hardware.h

+0 −18
Original line number Diff line number Diff line
@@ -36,28 +36,10 @@ 
#define io_v2p( x )             \

   ( (((x)&0x00ffffff) | (((x)&(0x30000000>>VIO_SHIFT))<<VIO_SHIFT)) + PIO_START )



#define CPU_SA1110_A0	(0)

#define CPU_SA1110_B0	(4)

#define CPU_SA1110_B1	(5)

#define CPU_SA1110_B2	(6)

#define CPU_SA1110_B4	(8)



#define CPU_SA1100_ID	(0x4401a110)

#define CPU_SA1100_MASK	(0xfffffff0)

#define CPU_SA1110_ID	(0x6901b110)

#define CPU_SA1110_MASK	(0xfffffff0)



#define __MREG(x)	IOMEM(io_p2v(x))



#ifndef __ASSEMBLY__



#include <asm/cputype.h>



#define CPU_REVISION	(read_cpuid_id() & 15)



#define cpu_is_sa1100()	((read_cpuid_id() & CPU_SA1100_MASK) == CPU_SA1100_ID)

#define cpu_is_sa1110()	((read_cpuid_id() & CPU_SA1110_MASK) == CPU_SA1110_ID)



# define __REG(x)	(*((volatile unsigned long __iomem *)io_p2v(x)))

# define __PREG(x)	(io_v2p((unsigned long)&(x)))

drivers/cpufreq/sa1110-cpufreq.c

+1 −1
Original line number Diff line number Diff line
@@ -159,7 +159,7 @@ sdram_calculate_timing(struct sdram_info *sd, u_int cpu_khz, 
	 * half speed or use delayed read latching (errata 13).

	 */

	if ((ns_to_cycles(sdram->tck, sd_khz) > 1) ||

	    (CPU_REVISION < CPU_SA1110_B2 && sd_khz < 62000))

	    (read_cpuid_revision() < ARM_CPU_REV_SA1110_B2 && sd_khz < 62000))

		sd_khz /= 2;



	sd->mdcnfg = MDCNFG & 0x007f007f;